| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _CONFIG_DB_MV7846MP_GP_H |
| 7 | #define _CONFIG_DB_MV7846MP_GP_H |
| 8 | |
| Tom Rini | 5155665 | 2021-08-21 13:50:14 -0400 | [diff] [blame] | 9 | #include <linux/sizes.h> |
| 10 | |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 11 | /* |
| 12 | * High Level Configuration Options (easy to change) |
| 13 | */ |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 14 | |
| Stefan Roese | 3dbf35c | 2015-08-06 14:27:36 +0200 | [diff] [blame] | 15 | /* |
| 16 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 17 | * for DDR ECC byte filling in the SPL before loading the main |
| 18 | * U-Boot into it. |
| 19 | */ |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 20 | |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 21 | /* I2C */ |
| Tom Rini | c188ed4 | 2022-12-04 10:04:09 -0500 | [diff] [blame] | 22 | #define CFG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 23 | |
| 24 | /* SPI NOR flash default params, used by sf commands */ |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 25 | |
| 26 | /* Environment in SPI NOR flash */ |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 27 | |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 28 | /* |
| 29 | * mv-common.h should be defined after CMD configs since it used them |
| 30 | * to enable certain macros |
| 31 | */ |
| 32 | #include "mv-common.h" |
| 33 | |
| Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 34 | /* |
| 35 | * Memory layout while starting into the bin_hdr via the |
| 36 | * BootROM: |
| 37 | * |
| 38 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) |
| 39 | * 0x4000.4030 bin_hdr start address |
| 40 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) |
| 41 | * 0x4007.fffc BootROM stack top |
| 42 | * |
| 43 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in |
| 44 | * L2 cache thus cannot be used. |
| 45 | */ |
| 46 | |
| Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 47 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ |
| Tom Rini | bb4dd96 | 2022-11-16 13:10:37 -0500 | [diff] [blame] | 48 | #define CFG_SYS_SDRAM_SIZE SZ_1G |
| Stefan Roese | 1a16a0c | 2015-01-19 11:33:47 +0100 | [diff] [blame] | 49 | |
| Stefan Roese | 9b1e231 | 2014-10-22 12:13:19 +0200 | [diff] [blame] | 50 | #endif /* _CONFIG_DB_MV7846MP_GP_H */ |