Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2006 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * Based on original work by |
| 6 | * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | /************************************************************************ |
| 28 | * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards |
| 29 | * |
| 30 | * The defines: |
| 31 | * CONFIG_P3M750 or |
| 32 | * CONFIG_P3M7448 |
| 33 | * are written into include/config.h by the "make xxx_config" command |
| 34 | ***********************************************************************/ |
| 35 | #ifndef __CONFIG_H |
| 36 | #define __CONFIG_H |
| 37 | |
| 38 | /*----------------------------------------------------------------------- |
| 39 | * High Level Configuration Options |
| 40 | *----------------------------------------------------------------------*/ |
| 41 | #define CONFIG_P3Mx /* used for both board versions */ |
| 42 | |
| 43 | #if defined (CONFIG_P3M750) |
| 44 | #define CONFIG_750FX /* 750GL/GX/FX */ |
| 45 | #define CFG_BOARD_NAME "P3M750" |
| 46 | #define CFG_BUS_HZ 100000000 |
| 47 | #define CFG_BUS_CLK CFG_BUS_HZ |
| 48 | #define CFG_TCLK 100000000 |
| 49 | #elif defined (CONFIG_P3M7448) |
| 50 | #define CONFIG_74xx |
| 51 | #define CFG_BOARD_NAME "P3M7448" |
| 52 | #define CFG_BUS_HZ 133333333 |
| 53 | #define CFG_BUS_CLK CFG_BUS_HZ |
| 54 | #define CFG_TCLK 133333333 |
| 55 | #endif |
| 56 | #define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */ |
| 57 | |
| 58 | /* which initialization functions to call for this board */ |
| 59 | #define CFG_BOARD_ASM_INIT 1 |
| 60 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
| 61 | #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ |
| 62 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 63 | |
| 64 | /*----------------------------------------------------------------------- |
| 65 | * Base addresses -- Note these are effective addresses where the |
| 66 | * actual resources get mapped (not physical addresses) |
| 67 | *----------------------------------------------------------------------*/ |
| 68 | #define CFG_SDRAM_BASE 0x00000000 |
| 69 | #ifdef CONFIG_P3M750 |
| 70 | #define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */ |
| 71 | #endif |
| 72 | |
| 73 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 74 | #if defined (CONFIG_P3M750) |
| 75 | #define CFG_FLASH_BASE 0xff800000 /* start of flash banks */ |
| 76 | #define CFG_BOOT_SIZE _8M /* boot flash */ |
| 77 | #elif defined (CONFIG_P3M7448) |
| 78 | #define CFG_FLASH_BASE 0xff000000 /* start of flash banks */ |
| 79 | #define CFG_BOOT_SIZE _16M /* boot flash */ |
| 80 | #endif |
| 81 | #define CFG_BOOT_SPACE CFG_FLASH_BASE /* BOOT_CS0 flash 0 */ |
| 82 | #define CFG_MONITOR_BASE 0xfff00000 |
| 83 | #define CFG_RESET_ADDRESS 0xfff00100 |
| 84 | #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ |
| 85 | #define CFG_MISC_REGION_BASE 0xf0000000 |
| 86 | |
| 87 | #define CFG_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ |
| 88 | #define CFG_GT_REGS 0xf1000000 /* GT Registers are mapped here */ |
| 89 | #define CFG_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ |
| 90 | |
| 91 | /*----------------------------------------------------------------------- |
| 92 | * Initial RAM & stack pointer (placed in internal SRAM) |
| 93 | *----------------------------------------------------------------------*/ |
| 94 | /* |
| 95 | * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS |
| 96 | * To an unused memory region. The stack will remain in cache until RAM |
| 97 | * is initialized |
| 98 | */ |
| 99 | #undef CFG_INIT_RAM_LOCK |
| 100 | #define CFG_INIT_RAM_ADDR 0x42000000 |
| 101 | #define CFG_INIT_RAM_END 0x1000 |
| 102 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */ |
| 103 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 104 | |
| 105 | |
| 106 | /*----------------------------------------------------------------------- |
| 107 | * Serial Port |
| 108 | *----------------------------------------------------------------------*/ |
| 109 | #define CONFIG_MPSC /* MV64460 Serial */ |
| 110 | #define CONFIG_MPSC_PORT 0 |
| 111 | #define CONFIG_BAUDRATE 115200 /* console baudrate */ |
| 112 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| 113 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
| 114 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 115 | |
| 116 | /*----------------------------------------------------------------------- |
| 117 | * Ethernet |
| 118 | *----------------------------------------------------------------------*/ |
| 119 | /* Change the default ethernet port, use this define (options: 0, 1, 2) */ |
| 120 | #define CFG_ETH_PORT ETH_0 |
| 121 | #define CONFIG_NET_MULTI |
| 122 | #define MV_ETH_DEVS 2 |
| 123 | #define CONFIG_PHY_RESET 1 /* reset phy upon startup */ |
| 124 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ |
| 125 | |
| 126 | /*----------------------------------------------------------------------- |
| 127 | * FLASH related |
| 128 | *----------------------------------------------------------------------*/ |
| 129 | #define CFG_FLASH_CFI /* The flash is CFI compatible */ |
| 130 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
| 131 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 132 | #define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ |
| 133 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
| 134 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ |
| 135 | #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ |
| 136 | #define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ |
| 137 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 138 | |
| 139 | #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
| 140 | #if defined (CONFIG_P3M750) |
| 141 | #define CFG_ENV_SECT_SIZE 0x20000 /* one sector (1 device)*/ |
| 142 | #elif defined (CONFIG_P3M7448) |
| 143 | #define CFG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ |
| 144 | #endif |
| 145 | #define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
| 146 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
| 147 | |
| 148 | /*----------------------------------------------------------------------- |
| 149 | * DDR SDRAM |
| 150 | *----------------------------------------------------------------------*/ |
| 151 | #define CONFIG_MV64460_ECC |
| 152 | |
| 153 | /*----------------------------------------------------------------------- |
| 154 | * I2C |
| 155 | *----------------------------------------------------------------------*/ |
| 156 | #define CFG_I2C_SPEED 100000 /* I2C speed default */ |
| 157 | |
| 158 | /* I2C RTC */ |
| 159 | #define CONFIG_RTC_M41T11 1 |
| 160 | #define CFG_I2C_RTC_ADDR 0x68 |
| 161 | #define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */ |
| 162 | |
| 163 | /*----------------------------------------------------------------------- |
| 164 | * PCI stuff |
| 165 | *----------------------------------------------------------------------*/ |
| 166 | #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ |
| 167 | #define PCI_HOST_FORCE 1 /* configure as pci host */ |
| 168 | #define PCI_HOST_AUTO 2 /* detected via arbiter enable */ |
| 169 | |
Stefan Roese | 46437f5 | 2007-01-18 11:54:52 +0100 | [diff] [blame] | 170 | #undef CONFIG_PCI /* include pci support */ |
| 171 | #ifdef CONFIG_PCI |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 172 | #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ |
| 173 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| 174 | #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ |
Stefan Roese | 46437f5 | 2007-01-18 11:54:52 +0100 | [diff] [blame] | 175 | #endif /* CONFIG_PCI */ |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 176 | |
| 177 | /* PCI MEMORY MAP section */ |
| 178 | #define CFG_PCI0_MEM_BASE 0x80000000 |
| 179 | #define CFG_PCI0_MEM_SIZE _128M |
| 180 | #define CFG_PCI1_MEM_BASE 0x88000000 |
| 181 | #define CFG_PCI1_MEM_SIZE _128M |
| 182 | |
| 183 | #define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE) |
| 184 | #define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE) |
| 185 | |
| 186 | /* PCI I/O MAP section */ |
| 187 | #define CFG_PCI0_IO_BASE 0xfa000000 |
| 188 | #define CFG_PCI0_IO_SIZE _16M |
| 189 | #define CFG_PCI1_IO_BASE 0xfb000000 |
| 190 | #define CFG_PCI1_IO_SIZE _16M |
| 191 | |
| 192 | #define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE) |
| 193 | #define CFG_PCI0_IO_SPACE_PCI 0x00000000 |
| 194 | #define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE) |
| 195 | #define CFG_PCI1_IO_SPACE_PCI 0x00000000 |
| 196 | |
| 197 | #define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE) |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 198 | #define CFG_PCI_IDSEL 0x30 |
| 199 | |
| 200 | #undef CONFIG_BOOTARGS |
| 201 | #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ |
| 202 | "netdev=eth0\0" \ |
| 203 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
| 204 | "nfsroot=${serverip}:${rootpath}\0" \ |
| 205 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
| 206 | "addip=setenv bootargs ${bootargs} " \ |
| 207 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ |
| 208 | ":${hostname}:${netdev}:off panic=1\0" \ |
| 209 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ |
| 210 | "flash_nfs=run nfsargs addip addtty;" \ |
| 211 | "bootm ${kernel_addr}\0" \ |
| 212 | "flash_self=run ramargs addip addtty;" \ |
| 213 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
| 214 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ |
| 215 | "bootm\0" \ |
| 216 | "rootpath=/opt/eldk/ppc_6xx\0" \ |
| 217 | "u-boot=p3mx/u-boot/u-boot.bin\0" \ |
| 218 | "load=tftp 100000 ${u-boot}\0" \ |
| 219 | "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ |
| 220 | "cp.b 100000 fff00000 40000;" \ |
| 221 | "setenv filesize;saveenv\0" \ |
| 222 | "upd=run load;run update\0" \ |
| 223 | "serverip=11.0.0.152\0" |
| 224 | |
| 225 | #if defined (CONFIG_P3M750) |
| 226 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 227 | CONFIG_EXTRA_ENV_SETTINGS_COMMON \ |
| 228 | "hostname=p3m750\0" \ |
| 229 | "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ |
| 230 | "kernel_addr=fc000000\0" \ |
| 231 | "ramdisk_addr=fc180000\0" \ |
| 232 | "vxfile=p3m750/vxWorks\0" \ |
| 233 | "vxuser=ddg\0" \ |
| 234 | "vxpass=ddg\0" \ |
| 235 | "vxtarget=target\0" \ |
| 236 | "vxflags=0x8\0" \ |
| 237 | "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ |
| 238 | "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ |
| 239 | "f=${vxflags}\0" |
| 240 | #elif defined (CONFIG_P3M7448) |
| 241 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 242 | CONFIG_EXTRA_ENV_SETTINGS_COMMON \ |
| 243 | "hostname=p3m7448\0" |
| 244 | #endif |
| 245 | |
| 246 | #if defined (CONFIG_P3M750) |
| 247 | #define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" |
| 248 | #elif defined (CONFIG_P3M7448) |
| 249 | #define CONFIG_BOOTCOMMAND " " |
| 250 | #endif |
| 251 | |
| 252 | #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ |
Jon Loeliger | c6d535a | 2007-07-09 21:57:31 -0500 | [diff] [blame] | 253 | |
| 254 | /* |
| 255 | * BOOTP options |
| 256 | */ |
| 257 | #define CONFIG_BOOTP_SUBNETMASK |
| 258 | #define CONFIG_BOOTP_GATEWAY |
| 259 | #define CONFIG_BOOTP_HOSTNAME |
| 260 | #define CONFIG_BOOTP_BOOTPATH |
| 261 | #define CONFIG_BOOTP_BOOTFILESIZE |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 262 | |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 263 | /* |
| 264 | * Command line configuration. |
| 265 | */ |
| 266 | #include <config_cmd_default.h> |
| 267 | |
| 268 | #define CONFIG_CMD_ASKENV |
| 269 | #define CONFIG_CMD_DATE |
| 270 | #define CONFIG_CMD_DIAG |
| 271 | #define CONFIG_CMD_ELF |
| 272 | #define CONFIG_CMD_I2C |
| 273 | #define CONFIG_CMD_IRQ |
| 274 | #define CONFIG_CMD_MII |
| 275 | #define CONFIG_CMD_NET |
| 276 | #define CONFIG_CMD_NFS |
| 277 | #define CONFIG_CMD_PING |
| 278 | #define CONFIG_CMD_REGINFO |
| 279 | #define CONFIG_CMD_PCI |
| 280 | #define CONFIG_CMD_CACHE |
| 281 | #define CONFIG_CMD_SDRAM |
| 282 | |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 283 | |
| 284 | /*----------------------------------------------------------------------- |
| 285 | * Miscellaneous configurable options |
| 286 | *----------------------------------------------------------------------*/ |
| 287 | #define CFG_HUSH_PARSER |
| 288 | #define CFG_PROMPT_HUSH_PS2 "> " |
| 289 | |
| 290 | #define CFG_LONGHELP /* undef to save memory */ |
| 291 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 292 | #if defined(CONFIG_CMD_KGDB) |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 293 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 294 | #else |
| 295 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 296 | #endif |
| 297 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 298 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 299 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 300 | |
| 301 | #define CFG_MEMTEST_START 0x0400000 /* memtest works on */ |
| 302 | #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ |
| 303 | |
| 304 | #define CFG_LOAD_ADDR 0x08000000 /* default load address */ |
| 305 | |
| 306 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 307 | |
| 308 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
| 309 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
| 310 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
| 311 | #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ |
| 312 | #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ |
| 313 | |
| 314 | /*----------------------------------------------------------------------- |
| 315 | * Marvell MV64460 config settings |
| 316 | *----------------------------------------------------------------------*/ |
| 317 | /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ |
| 318 | #if defined (CONFIG_P3M750) |
| 319 | #define CFG_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ |
| 320 | #elif defined (CONFIG_P3M7448) |
| 321 | #define CFG_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ |
| 322 | #endif |
| 323 | |
| 324 | /* |
| 325 | * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) |
| 326 | * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) |
| 327 | * MPP[2] NC |
| 328 | * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) |
| 329 | * MPP[4] PCI Monarch# GPIO IN Connected to P12 |
| 330 | * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) |
| 331 | * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 |
| 332 | * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 |
| 333 | * MPP[8] Reserved Do not use |
| 334 | * MPP[9] Reserved Do not use |
| 335 | * MPP[10] Reserved Do not use |
| 336 | * MPP[11] Reserved Do not use |
| 337 | * MPP[12] Phy 0 Interrupt Int IN |
| 338 | * MPP[13] Phy 1 Interrupt Int IN |
| 339 | * MPP[14] NC |
| 340 | * MPP[15] NC |
| 341 | * MPP[16] PCI Interrupt C Int IN Connected to P11 |
| 342 | * MPP[17] PCI Interrupt D Int IN Connected to P11 |
| 343 | * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] |
| 344 | * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic |
| 345 | * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog |
| 346 | * MPP[21] NC |
| 347 | * MPP[22] GP LED Green GPIO OUT |
| 348 | * MPP[23] GP LED Red GPIO OUT |
| 349 | * MPP[24] Watchdog NMI# Int OUT |
| 350 | * MPP[25] NC |
| 351 | * MPP[26] NC |
| 352 | * MPP[27] PCI Interrupt A Int IN Connected to P11 |
| 353 | * MPP[28] NC |
| 354 | * MPP[29] PCI Interrupt B Int IN Connected to P11 |
| 355 | * MPP[30] Module reset GPIO OUT Board reset |
| 356 | * MPP[31] PCI EReady GPIO IN Connected to P12 |
| 357 | */ |
| 358 | #define CFG_MPP_CONTROL_0 0x00303022 |
| 359 | #define CFG_MPP_CONTROL_1 0x00000000 |
| 360 | #define CFG_MPP_CONTROL_2 0x00004000 |
| 361 | #define CFG_MPP_CONTROL_3 0x00000004 |
| 362 | #define CFG_GPP_LEVEL_CONTROL 0x280730D0 |
| 363 | |
| 364 | /*---------------------------------------------------------------------- |
| 365 | * Initial BAT mappings |
| 366 | */ |
| 367 | |
| 368 | /* NOTES: |
| 369 | * 1) GUARDED and WRITE_THRU not allowed in IBATS |
| 370 | * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT |
| 371 | */ |
| 372 | /* SDRAM */ |
| 373 | #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 374 | #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 375 | #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) |
| 376 | #define CFG_DBAT0U CFG_IBAT0U |
| 377 | |
| 378 | /* init ram */ |
| 379 | #define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 380 | #define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) |
| 381 | #define CFG_DBAT1L CFG_IBAT1L |
| 382 | #define CFG_DBAT1U CFG_IBAT1U |
| 383 | |
| 384 | /* PCI0, PCI1 in one BAT */ |
| 385 | #define CFG_IBAT2L BATL_NO_ACCESS |
| 386 | #define CFG_IBAT2U CFG_DBAT2U |
| 387 | #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
| 388 | #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 389 | |
| 390 | /* GT regs, bootrom, all the devices, PCI I/O */ |
| 391 | #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) |
| 392 | #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) |
| 393 | #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) |
| 394 | #define CFG_DBAT3U CFG_IBAT3U |
| 395 | |
| 396 | #define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 397 | #define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
| 398 | #define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 399 | #define CFG_DBAT4U CFG_IBAT4U |
| 400 | |
| 401 | /* set rest out of range for Linux !!!!!!!!!!! */ |
| 402 | |
| 403 | /* IBAT5 and DBAT5 */ |
| 404 | #define CFG_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 405 | #define CFG_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 406 | #define CFG_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 407 | #define CFG_DBAT5U CFG_IBAT5U |
| 408 | |
| 409 | /* IBAT6 and DBAT6 */ |
| 410 | #define CFG_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 411 | #define CFG_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 412 | #define CFG_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 413 | #define CFG_DBAT6U CFG_IBAT6U |
| 414 | |
| 415 | /* IBAT7 and DBAT7 */ |
| 416 | #define CFG_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 417 | #define CFG_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
| 418 | #define CFG_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 419 | #define CFG_DBAT7U CFG_IBAT7U |
| 420 | |
| 421 | /* |
| 422 | * For booting Linux, the board info and command line data |
| 423 | * have to be in the first 8 MB of memory, since this is |
| 424 | * the maximum mapped by the Linux kernel during initialization. |
| 425 | */ |
| 426 | #define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ |
| 427 | #define CFG_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ |
| 428 | |
| 429 | /*----------------------------------------------------------------------- |
| 430 | * Cache Configuration |
| 431 | */ |
| 432 | #define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ |
Jon Loeliger | aa2d2c2 | 2007-07-04 22:33:17 -0500 | [diff] [blame] | 433 | #if defined(CONFIG_CMD_KGDB) |
Stefan Roese | 45993ea | 2006-11-29 15:42:37 +0100 | [diff] [blame] | 434 | #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 435 | #endif |
| 436 | |
| 437 | /*----------------------------------------------------------------------- |
| 438 | * L2CR setup -- make sure this is right for your board! |
| 439 | * look in include/mpc74xx.h for the defines used here |
| 440 | */ |
| 441 | #define CFG_L2 |
| 442 | |
| 443 | #if defined (CONFIG_750CX) || defined (CONFIG_750FX) |
| 444 | #define L2_INIT 0 |
| 445 | #else |
| 446 | #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ |
| 447 | L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) |
| 448 | #endif |
| 449 | |
| 450 | #define L2_ENABLE (L2_INIT | L2CR_L2E) |
| 451 | |
| 452 | /* |
| 453 | * Internal Definitions |
| 454 | * |
| 455 | * Boot Flags |
| 456 | */ |
| 457 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 458 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 459 | |
| 460 | #endif /* __CONFIG_H */ |