| Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010 |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; either version 2 of |
| 8 | * the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 18 | * MA 02111-1307 USA |
| 19 | */ |
| 20 | |
| 21 | #ifndef _PPC460EX_GT_H_ |
| 22 | #define _PPC460EX_GT_H_ |
| 23 | |
| 24 | #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ |
| 25 | |
| 26 | #define CONFIG_NAND_NDFC |
| 27 | |
| Stefan Roese | 95ca5fa | 2010-09-11 09:31:43 +0200 | [diff] [blame] | 28 | /* |
| 29 | * Some SoC specific registers |
| 30 | */ |
| 31 | |
| 32 | #define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000B00) |
| 33 | #define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000C00) |
| 34 | |
| 35 | /* DCR */ |
| 36 | #define AHB_TOP 0x00a4 |
| 37 | #define AHB_BOT 0x00a5 |
| 38 | |
| 39 | /* SDR */ |
| 40 | #define SDR0_PCI0 0x01c0 |
| 41 | #define SDR0_AHB_CFG 0x0370 |
| 42 | #define SDR0_USB2HOST_CFG 0x0371 |
| 43 | #define SDR0_ETH_PLL 0x4102 |
| 44 | #define SDR0_ETH_CFG 0x4103 |
| 45 | #define SDR0_ETH_STS 0x4104 |
| 46 | |
| 47 | /* |
| 48 | * Register bits and masks |
| 49 | */ |
| 50 | #define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) |
| 51 | #define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) |
| 52 | |
| 53 | /* CUST0 Customer Configuration Register0 */ |
| 54 | #define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ |
| 55 | #define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ |
| 56 | #define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ |
| 57 | #define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ |
| 58 | |
| 59 | #define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ |
| 60 | #define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ |
| 61 | #define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ |
| 62 | |
| 63 | #define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ |
| 64 | #define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ |
| 65 | #define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ |
| 66 | |
| 67 | #define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ |
| 68 | #define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) |
| 69 | #define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) |
| 70 | |
| 71 | #define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ |
| 72 | #define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) |
| 73 | #define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) |
| 74 | |
| 75 | #define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ |
| 76 | #define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ |
| 77 | #define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ |
| 78 | |
| 79 | #define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ |
| 80 | #define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ |
| 81 | #define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ |
| 82 | |
| 83 | #define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ |
| 84 | #define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) |
| 85 | #define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) |
| 86 | |
| 87 | #define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ |
| 88 | #define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ |
| 89 | #define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ |
| 90 | #define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ |
| 91 | #define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ |
| 92 | #define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ |
| 93 | #define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ |
| 94 | |
| 95 | /* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ |
| 96 | #define SDR0_ETH_PLL_PLLLOCK 0x80000000 /* Ethernet PLL lock indication */ |
| 97 | |
| 98 | /* Ethernet Configuration Register (SDR0_ETH_CFG) */ |
| 99 | #define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback |
| 100 | enable */ |
| 101 | #define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback |
| 102 | enable */ |
| 103 | #define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback |
| 104 | enable */ |
| 105 | #define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback |
| 106 | enable */ |
| 107 | #define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */ |
| 108 | #define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */ |
| 109 | #define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */ |
| 110 | #define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */ |
| 111 | #define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */ |
| 112 | #define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */ |
| 113 | #define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/ |
| 114 | #define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/ |
| 115 | #define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/ |
| 116 | #define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/ |
| 117 | #define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */ |
| 118 | #define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */ |
| 119 | #define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/ |
| 120 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */ |
| 121 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */ |
| 122 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */ |
| 123 | #define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */ |
| 124 | #define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge |
| 125 | selector */ |
| 126 | #define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge |
| 127 | selector */ |
| 128 | |
| 129 | #define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ |
| 130 | #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ |
| 131 | #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ |
| 132 | #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ |
| 133 | #define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ |
| 134 | transmitter 0 */ |
| 135 | #define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ |
| 136 | transmitter 1 */ |
| 137 | #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ |
| 138 | #define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ |
| 139 | #define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ |
| 140 | #define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ |
| 141 | #define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ |
| 142 | #define SDR0_SRST0_PCI 0x00100000 /* PCI */ |
| 143 | #define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ |
| 144 | #define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ |
| 145 | #define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/ |
| 146 | #define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/ |
| 147 | #define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/ |
| 148 | #define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ |
| 149 | #define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ |
| 150 | #define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ |
| 151 | #define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ |
| 152 | transmitter 2 */ |
| 153 | #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ |
| 154 | #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ |
| 155 | #define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ |
| 156 | #define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ |
| 157 | transmitter 3 */ |
| 158 | #define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ |
| 159 | |
| 160 | #define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ |
| 161 | #define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ |
| 162 | #define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ |
| 163 | #define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ |
| 164 | #define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ |
| 165 | #define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access |
| 166 | controller 0 */ |
| 167 | #define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access |
| 168 | controller 1 */ |
| 169 | #define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access |
| 170 | controller 2 */ |
| 171 | #define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access |
| 172 | controller 3 */ |
| 173 | #define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ |
| 174 | #define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ |
| 175 | #define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ |
| 176 | #define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ |
| 177 | #define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ |
| 178 | #define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ |
| 179 | #define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and |
| 180 | serdes */ |
| 181 | #define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ |
| 182 | #define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ |
| 183 | #define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ |
| 184 | #define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ |
| 185 | #define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ |
| 186 | #define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ |
| 187 | #define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ |
| 188 | #define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ |
| 189 | #define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ |
| 190 | #define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ |
| 191 | #define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ |
| 192 | #define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ |
| 193 | #define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ |
| 194 | #define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ |
| 195 | #define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ |
| 196 | #define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ |
| 197 | |
| 198 | #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ |
| 199 | #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ |
| 200 | #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ |
| 201 | #define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ |
| 202 | #define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ |
| 203 | #define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ |
| 204 | #define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ |
| 205 | |
| 206 | #define CPR0_ICFG_RLI_MASK 0x80000000 |
| 207 | |
| 208 | #define CPR0_PLLC_RST 0x80000000 |
| 209 | #define CPR0_PLLC_ENG 0x40000000 |
| 210 | |
| 211 | #define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) |
| 212 | #define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) |
| 213 | |
| 214 | #endif /* _PPC460EX_GT_H_ */ |