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Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Jaehoon Chung <jh80.chung@samsung.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +00006 */
7
8#include <common.h>
9#include <malloc.h>
10#include <sdhci.h>
Piotr Wilczek12cf19e2014-03-07 14:59:41 +010011#include <fdtdec.h>
12#include <libfdt.h>
13#include <asm/gpio.h>
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000014#include <asm/arch/mmc.h>
Jaehoon Chungb1929ea2012-08-30 16:24:11 +000015#include <asm/arch/clk.h>
Piotr Wilczek12cf19e2014-03-07 14:59:41 +010016#include <errno.h>
17#ifdef CONFIG_OF_CONTROL
18#include <asm/arch/pinmux.h>
19#endif
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000020
21static char *S5P_NAME = "SAMSUNG SDHCI";
22static void s5p_sdhci_set_control_reg(struct sdhci_host *host)
23{
24 unsigned long val, ctrl;
25 /*
26 * SELCLKPADDS[17:16]
27 * 00 = 2mA
28 * 01 = 4mA
29 * 10 = 7mA
30 * 11 = 9mA
31 */
32 sdhci_writel(host, SDHCI_CTRL4_DRIVE_MASK(0x3), SDHCI_CONTROL4);
33
34 val = sdhci_readl(host, SDHCI_CONTROL2);
35 val &= SDHCI_CTRL2_SELBASECLK_SHIFT;
36
37 val |= SDHCI_CTRL2_ENSTAASYNCCLR |
38 SDHCI_CTRL2_ENCMDCNFMSK |
39 SDHCI_CTRL2_ENFBCLKRX |
40 SDHCI_CTRL2_ENCLKOUTHOLD;
41
42 sdhci_writel(host, val, SDHCI_CONTROL2);
43
44 /*
45 * FCSEL3[31] FCSEL2[23] FCSEL1[15] FCSEL0[7]
46 * FCSel[1:0] : Rx Feedback Clock Delay Control
47 * Inverter delay means10ns delay if SDCLK 50MHz setting
48 * 01 = Delay1 (basic delay)
49 * 11 = Delay2 (basic delay + 2ns)
50 * 00 = Delay3 (inverter delay)
51 * 10 = Delay4 (inverter delay + 2ns)
52 */
Jaehoon Chungb36cbac2012-08-30 16:24:08 +000053 val = SDHCI_CTRL3_FCSEL0 | SDHCI_CTRL3_FCSEL1;
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000054 sdhci_writel(host, val, SDHCI_CONTROL3);
55
56 /*
57 * SELBASECLK[5:4]
58 * 00/01 = HCLK
59 * 10 = EPLL
60 * 11 = XTI or XEXTCLK
61 */
62 ctrl = sdhci_readl(host, SDHCI_CONTROL2);
63 ctrl &= ~SDHCI_CTRL2_SELBASECLK_MASK(0x3);
64 ctrl |= SDHCI_CTRL2_SELBASECLK_MASK(0x2);
65 sdhci_writel(host, ctrl, SDHCI_CONTROL2);
66}
67
Jaehoon Chungb494ac82014-05-16 13:59:59 +090068static int s5p_sdhci_core_init(struct sdhci_host *host)
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000069{
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000070 host->name = S5P_NAME;
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000071
Jaehoon Chungb36cbac2012-08-30 16:24:08 +000072 host->quirks = SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_VOLTAGE |
Tushar Behera0fba4c22012-09-20 20:31:57 +000073 SDHCI_QUIRK_BROKEN_R1B | SDHCI_QUIRK_32BIT_DMA_ADDR |
Jaehoon Chung46e627c2013-07-19 17:44:49 +090074 SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_USE_WIDE8;
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000075 host->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
Jaehoon Chungb36cbac2012-08-30 16:24:08 +000076 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000077
78 host->set_control_reg = &s5p_sdhci_set_control_reg;
Jaehoon Chungb1929ea2012-08-30 16:24:11 +000079 host->set_clock = set_mmc_clk;
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000080
81 host->host_caps = MMC_MODE_HC;
Jaehoon Chungb494ac82014-05-16 13:59:59 +090082 if (host->bus_width == 8)
Jaehoon Chung46e627c2013-07-19 17:44:49 +090083 host->host_caps |= MMC_MODE_8BIT;
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000084
Jaehoon Chung0c3c2552012-12-13 20:07:12 +000085 return add_sdhci(host, 52000000, 400000);
Jaehoon Chungb0b0c9d2012-04-23 02:36:28 +000086}
Piotr Wilczek12cf19e2014-03-07 14:59:41 +010087
Jaehoon Chungb494ac82014-05-16 13:59:59 +090088int s5p_sdhci_init(u32 regbase, int index, int bus_width)
89{
90 struct sdhci_host *host = malloc(sizeof(struct sdhci_host));
91 if (!host) {
92 printf("sdhci__host malloc fail!\n");
93 return 1;
94 }
95 host->ioaddr = (void *)regbase;
96 host->index = index;
97 host->bus_width = bus_width;
98
99 return s5p_sdhci_core_init(host);
100}
101
Piotr Wilczek12cf19e2014-03-07 14:59:41 +0100102#ifdef CONFIG_OF_CONTROL
103struct sdhci_host sdhci_host[SDHCI_MAX_HOSTS];
104
105static int do_sdhci_init(struct sdhci_host *host)
106{
107 int dev_id, flag;
108 int err = 0;
109
110 flag = host->bus_width == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
111 dev_id = host->index + PERIPH_ID_SDMMC0;
112
113 if (fdt_gpio_isvalid(&host->pwr_gpio)) {
114 gpio_direction_output(host->pwr_gpio.gpio, 1);
115 err = exynos_pinmux_config(dev_id, flag);
116 if (err) {
117 debug("MMC not configured\n");
118 return err;
119 }
120 }
121
122 if (fdt_gpio_isvalid(&host->cd_gpio)) {
123 gpio_direction_output(host->cd_gpio.gpio, 0xf);
124 if (gpio_get_value(host->cd_gpio.gpio))
125 return -ENODEV;
126
127 err = exynos_pinmux_config(dev_id, flag);
128 if (err) {
129 printf("external SD not configured\n");
130 return err;
131 }
132 }
133
Jaehoon Chungb494ac82014-05-16 13:59:59 +0900134 return s5p_sdhci_core_init(host);
Piotr Wilczek12cf19e2014-03-07 14:59:41 +0100135}
136
137static int sdhci_get_config(const void *blob, int node, struct sdhci_host *host)
138{
139 int bus_width, dev_id;
140 unsigned int base;
141
142 /* Get device id */
143 dev_id = pinmux_decode_periph_id(blob, node);
144 if (dev_id < PERIPH_ID_SDMMC0 && dev_id > PERIPH_ID_SDMMC3) {
145 debug("MMC: Can't get device id\n");
146 return -1;
147 }
148 host->index = dev_id - PERIPH_ID_SDMMC0;
149
150 /* Get bus width */
151 bus_width = fdtdec_get_int(blob, node, "samsung,bus-width", 0);
152 if (bus_width <= 0) {
153 debug("MMC: Can't get bus-width\n");
154 return -1;
155 }
156 host->bus_width = bus_width;
157
158 /* Get the base address from the device node */
159 base = fdtdec_get_addr(blob, node, "reg");
160 if (!base) {
161 debug("MMC: Can't get base address\n");
162 return -1;
163 }
164 host->ioaddr = (void *)base;
165
166 fdtdec_decode_gpio(blob, node, "pwr-gpios", &host->pwr_gpio);
167 fdtdec_decode_gpio(blob, node, "cd-gpios", &host->cd_gpio);
168
169 return 0;
170}
171
172static int process_nodes(const void *blob, int node_list[], int count)
173{
174 struct sdhci_host *host;
175 int i, node;
176
177 debug("%s: count = %d\n", __func__, count);
178
179 /* build sdhci_host[] for each controller */
180 for (i = 0; i < count; i++) {
181 node = node_list[i];
182 if (node <= 0)
183 continue;
184
185 host = &sdhci_host[i];
186
187 if (sdhci_get_config(blob, node, host)) {
188 printf("%s: failed to decode dev %d\n", __func__, i);
189 return -1;
190 }
191 do_sdhci_init(host);
192 }
193 return 0;
194}
195
196int exynos_mmc_init(const void *blob)
197{
198 int count;
199 int node_list[SDHCI_MAX_HOSTS];
200
201 count = fdtdec_find_aliases_for_id(blob, "mmc",
202 COMPAT_SAMSUNG_EXYNOS_MMC, node_list,
203 SDHCI_MAX_HOSTS);
204
205 process_nodes(blob, node_list, count);
206
207 return 1;
208}
209#endif