blob: 1a304bab212064ba416734fdedc80b0dcdf71800 [file] [log] [blame]
Wenyou Yang8c772bd2016-07-20 17:55:12 +08001/*
2 * Copyright (C) 2016 Atmel Corporation
3 * Wenyou.Yang <wenyou.yang@atmel.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <clk-uclass.h>
10#include <dm/device.h>
11#include <dm/util.h>
12#include <linux/io.h>
13#include <mach/at91_pmc.h>
14#include "pmc.h"
15
16DECLARE_GLOBAL_DATA_PTR;
17
18#define H32MX_MAX_FREQ 90000000
19
20static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
21{
22 struct pmc_platdata *plat = dev_get_platdata(clk->dev);
23 struct at91_pmc *pmc = plat->reg_base;
24 ulong rate = gd->arch.mck_rate_hz;
25
26 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
27 rate /= 2;
28
29 if (rate > H32MX_MAX_FREQ)
30 dm_warn("H32MX clock is too fast\n");
31
32 return rate;
33}
34
35static struct clk_ops sama5d4_h32mx_clk_ops = {
36 .get_rate = sama5d4_h32mx_clk_get_rate,
37};
38
39static int sama5d4_h32mx_clk_probe(struct udevice *dev)
40{
41 return at91_pmc_core_probe(dev);
42}
43
44static const struct udevice_id sama5d4_h32mx_clk_match[] = {
45 { .compatible = "atmel,sama5d4-clk-h32mx" },
46 {}
47};
48
49U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
50 .name = "sama5d4-h32mx-clk",
51 .id = UCLASS_CLK,
52 .of_match = sama5d4_h32mx_clk_match,
53 .probe = sama5d4_h32mx_clk_probe,
54 .platdata_auto_alloc_size = sizeof(struct pmc_platdata),
55 .ops = &sama5d4_h32mx_clk_ops,
56};