| Mario Six | 98d7eaa | 2019-01-21 09:18:14 +0100 | [diff] [blame] | 1 | menu "LCRR - Clock Ratio Register register" |
| 2 | |
| 3 | if !ARCH_MPC8309 && !ARCH_MPC831X && !ARCH_MPC832X |
| 4 | |
| 5 | choice |
| 6 | prompt "DLL bypass" |
| 7 | |
| 8 | config LCRR_DBYP_UNSET |
| 9 | bool "Don't set value" |
| 10 | |
| 11 | config LCRR_DBYP_PLL_ENABLED |
| 12 | bool "PLL enabled" |
| 13 | |
| 14 | config LCRR_DBYP_PLL_BYPASSED |
| 15 | bool "PLL bypassed" |
| 16 | |
| 17 | endchoice |
| 18 | |
| 19 | endif |
| 20 | |
| 21 | if ARCH_MPC834X || ARCH_MPC8360 |
| 22 | |
| 23 | choice |
| 24 | prompt "Additional delay cycles for SDRAM control signals" |
| 25 | |
| 26 | config LCRR_BUFCMDC_UNSET |
| 27 | bool "Don't set value" |
| 28 | |
| 29 | config LCRR_BUFCMDC_4 |
| 30 | bool "4" |
| 31 | |
| 32 | config LCRR_BUFCMDC_1 |
| 33 | bool "1" |
| 34 | |
| 35 | config LCRR_BUFCMDC_2 |
| 36 | bool "2" |
| 37 | |
| 38 | config LCRR_BUFCMDC_3 |
| 39 | bool "3" |
| 40 | |
| 41 | endchoice |
| 42 | |
| 43 | choice |
| 44 | prompt "Extended CAS latency" |
| 45 | |
| 46 | config LCRR_ECL_UNSET |
| 47 | bool "Don't set value" |
| 48 | |
| 49 | config LCRR_ECL_4 |
| 50 | bool "4" |
| 51 | |
| 52 | config LCRR_ECL_5 |
| 53 | bool "5" |
| 54 | |
| 55 | config LCRR_ECL_6 |
| 56 | bool "6" |
| 57 | |
| 58 | config LCRR_ECL_7 |
| 59 | bool "7" |
| 60 | |
| 61 | endchoice |
| 62 | |
| 63 | endif # ARCH_MPC834X || ARCH_MPC8360 |
| 64 | |
| 65 | if !ARCH_MPC8308 |
| 66 | |
| 67 | choice |
| 68 | prompt "External address delay cycles" |
| 69 | |
| 70 | config LCRR_EADC_UNSET |
| 71 | bool "Don't set value" |
| 72 | |
| 73 | config LCRR_EADC_4 |
| 74 | bool "4" |
| 75 | |
| 76 | config LCRR_EADC_1 |
| 77 | bool "1" |
| 78 | |
| 79 | config LCRR_EADC_2 |
| 80 | bool "2" |
| 81 | |
| 82 | config LCRR_EADC_3 |
| 83 | bool "3" |
| 84 | |
| 85 | endchoice |
| 86 | |
| 87 | endif # !ARCH_MPC8308 |
| 88 | |
| 89 | choice |
| 90 | prompt "System clock divider" |
| 91 | |
| 92 | config LCRR_CLKDIV_UNSET |
| 93 | bool "Don't set value" |
| 94 | |
| 95 | config LCRR_CLKDIV_2 |
| 96 | bool "2" |
| 97 | |
| 98 | config LCRR_CLKDIV_4 |
| 99 | bool "4" |
| 100 | |
| 101 | config LCRR_CLKDIV_8 |
| 102 | bool "8" |
| 103 | |
| 104 | endchoice |
| 105 | |
| 106 | config LCRR_DBYP |
| 107 | hex |
| 108 | default 0x0 if LCRR_DBYP_UNSET || LCRR_DBYP_PLL_ENABLED |
| 109 | default 0x80000000 if LCRR_DBYP_PLL_BYPASSED |
| 110 | |
| 111 | config LCRR_BUFCMDC |
| 112 | hex |
| 113 | default 0x0 if LCRR_BUFCMDC_4 || LCRR_BUFCMDC_UNSET |
| 114 | default 0x10000000 if LCRR_BUFCMDC_1 |
| 115 | default 0x20000000 if LCRR_BUFCMDC_2 |
| 116 | default 0x30000000 if LCRR_BUFCMDC_3 |
| 117 | |
| 118 | config LCRR_ECL |
| 119 | hex |
| 120 | default 0x0 if LCRR_ECL_4 || LCRR_ECL_UNSET |
| 121 | default 0x1000000 if LCRR_ECL_5 |
| 122 | default 0x2000000 if LCRR_ECL_6 |
| 123 | default 0x3000000 if LCRR_ECL_7 |
| 124 | |
| 125 | config LCRR_EADC |
| 126 | hex |
| 127 | default 0x0 if LCRR_EADC_4 || LCRR_EADC_UNSET |
| 128 | default 0x10000 if LCRR_EADC_1 |
| 129 | default 0x20000 if LCRR_EADC_2 |
| 130 | default 0x30000 if LCRR_EADC_3 |
| 131 | |
| 132 | config LCRR_CLKDIV |
| 133 | hex |
| 134 | default 0x0 if LCRR_CLKDIV_UNSET |
| 135 | default 0x2 if LCRR_CLKDIV_2 |
| 136 | default 0x4 if LCRR_CLKDIV_4 |
| 137 | default 0x8 if LCRR_CLKDIV_8 |
| 138 | |
| 139 | endmenu |