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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass030777d2017-01-16 07:03:56 -07002/*
3 * Copyright (c) 2016 Google, Inc
Simon Glass030777d2017-01-16 07:03:56 -07004 */
5
Simon Glass3a1d96f2023-07-15 21:39:11 -06006#define LOG_CATEGORY LOGC_BOOT
7
Simon Glass030777d2017-01-16 07:03:56 -07008#include <common.h>
Simon Glass1d91ba72019-11-14 12:57:37 -07009#include <cpu_func.h>
Simon Glass030777d2017-01-16 07:03:56 -070010#include <debug_uart.h>
Simon Glass0b3c5762019-10-20 21:37:49 -060011#include <dm.h>
Simon Glassf11478f2019-12-28 10:45:07 -070012#include <hang.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060013#include <image.h>
Simon Glass97589732020-05-10 11:40:02 -060014#include <init.h>
Simon Glass9b61c7c2019-11-14 12:57:41 -070015#include <irq_func.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
Simon Glass7cf5fe02019-05-02 10:52:12 -060017#include <malloc.h>
Simon Glass030777d2017-01-16 07:03:56 -070018#include <spl.h>
Simon Glass0b3c5762019-10-20 21:37:49 -060019#include <syscon.h>
Simon Glasse50c4552023-07-15 21:39:01 -060020#include <vesa.h>
Simon Glass030777d2017-01-16 07:03:56 -070021#include <asm/cpu.h>
Simon Glass0b3c5762019-10-20 21:37:49 -060022#include <asm/cpu_common.h>
Simon Glassfc557362022-03-04 08:43:05 -070023#include <asm/fsp2/fsp_api.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060024#include <asm/global_data.h>
Simon Glassfb842432023-07-15 21:38:36 -060025#include <asm/mp.h>
Simon Glass7cf5fe02019-05-02 10:52:12 -060026#include <asm/mrccache.h>
Simon Glass030777d2017-01-16 07:03:56 -070027#include <asm/mtrr.h>
Simon Glass0b3c5762019-10-20 21:37:49 -060028#include <asm/pci.h>
Simon Glass030777d2017-01-16 07:03:56 -070029#include <asm/processor.h>
Simon Glass7dc0a452023-07-30 11:16:01 -060030#include <asm/qemu.h>
Simon Glass19da9c42019-09-25 08:11:39 -060031#include <asm/spl.h>
Simon Glass030777d2017-01-16 07:03:56 -070032#include <asm-generic/sections.h>
33
34DECLARE_GLOBAL_DATA_PTR;
35
Simon Glassfc557362022-03-04 08:43:05 -070036__weak int fsp_setup_pinctrl(void *ctx, struct event *event)
Bin Meng2240fde2017-01-18 03:32:53 -080037{
38 return 0;
39}
40
Simon Glass0b3c5762019-10-20 21:37:49 -060041#ifdef CONFIG_TPL
42
43static int set_max_freq(void)
44{
45 if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
46 /*
47 * Burst Mode has been factory-configured as disabled and is not
48 * available in this physical processor package
49 */
50 debug("Burst Mode is factory-disabled\n");
51 return -ENOENT;
52 }
53
54 /* Enable burst mode */
55 cpu_set_burst_mode(true);
56
57 /* Enable speed step */
58 cpu_set_eist(true);
59
60 /* Set P-State ratio */
61 cpu_set_p_state_to_turbo_ratio();
62
63 return 0;
64}
65#endif
66
Simon Glass030777d2017-01-16 07:03:56 -070067static int x86_spl_init(void)
68{
Simon Glassb3f351f2023-07-15 21:39:13 -060069 struct udevice *dev;
70
Simon Glass7cf5fe02019-05-02 10:52:12 -060071#ifndef CONFIG_TPL
Simon Glass030777d2017-01-16 07:03:56 -070072 /*
73 * TODO(sjg@chromium.org): We use this area of RAM for the stack
74 * and global_data in SPL. Once U-Boot starts up and releocates it
75 * is not needed. We could make this a CONFIG option or perhaps
Simon Glass72cc5382022-10-20 18:22:39 -060076 * place it immediately below CONFIG_TEXT_BASE.
Simon Glass030777d2017-01-16 07:03:56 -070077 */
Simon Glassdae11532020-04-30 21:21:42 -060078 __maybe_unused char *ptr = (char *)0x110000;
Simon Glass0b3c5762019-10-20 21:37:49 -060079#else
80 struct udevice *punit;
Simon Glass7cf5fe02019-05-02 10:52:12 -060081#endif
Simon Glass030777d2017-01-16 07:03:56 -070082 int ret;
83
Simon Glass3a1d96f2023-07-15 21:39:11 -060084 log_debug("x86 spl starting\n");
Simon Glass81f14622019-10-20 21:37:55 -060085 if (IS_ENABLED(TPL))
86 ret = x86_cpu_reinit_f();
87 else
88 ret = x86_cpu_init_f();
Simon Glass030777d2017-01-16 07:03:56 -070089 ret = spl_init();
90 if (ret) {
Simon Glass3a1d96f2023-07-15 21:39:11 -060091 log_debug("spl_init() failed (err=%d)\n", ret);
Simon Glass030777d2017-01-16 07:03:56 -070092 return ret;
93 }
Simon Glass030777d2017-01-16 07:03:56 -070094 ret = arch_cpu_init();
95 if (ret) {
Simon Glass3a1d96f2023-07-15 21:39:11 -060096 log_debug("arch_cpu_init() failed (err=%d)\n", ret);
Simon Glass030777d2017-01-16 07:03:56 -070097 return ret;
98 }
Simon Glass7cf5fe02019-05-02 10:52:12 -060099#ifndef CONFIG_TPL
Simon Glassfc557362022-03-04 08:43:05 -0700100 ret = fsp_setup_pinctrl(NULL, NULL);
Simon Glass030777d2017-01-16 07:03:56 -0700101 if (ret) {
Simon Glass3a1d96f2023-07-15 21:39:11 -0600102 log_debug("fsp_setup_pinctrl() failed (err=%d)\n", ret);
Simon Glass030777d2017-01-16 07:03:56 -0700103 return ret;
104 }
Simon Glass7cf5fe02019-05-02 10:52:12 -0600105#endif
Simon Glassfbfb4762023-07-15 21:39:00 -0600106 /*
107 * spl_board_init() below sets up the console if enabled. If it isn't,
108 * do it here. We cannot call this twice since it results in a double
109 * banner and CI tests fail.
110 */
111 if (!IS_ENABLED(CONFIG_SPL_BOARD_INIT))
112 preloader_console_init();
Simon Glass2f002162021-03-15 18:11:18 +1300113#if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU)
Simon Glass030777d2017-01-16 07:03:56 -0700114 ret = print_cpuinfo();
115 if (ret) {
Simon Glass3a1d96f2023-07-15 21:39:11 -0600116 log_debug("print_cpuinfo() failed (err=%d)\n", ret);
Simon Glass030777d2017-01-16 07:03:56 -0700117 return ret;
118 }
Simon Glass7cf5fe02019-05-02 10:52:12 -0600119#endif
Simon Glassb3f351f2023-07-15 21:39:13 -0600120 /* probe the LPC so we get the GPIO_BASE set up correctly */
121 ret = uclass_first_device_err(UCLASS_LPC, &dev);
122 if (ret && ret != -ENODEV) {
123 log_debug("lpc probe failed\n");
124 return ret;
125 }
126
Simon Glass030777d2017-01-16 07:03:56 -0700127 ret = dram_init();
128 if (ret) {
Simon Glass3a1d96f2023-07-15 21:39:11 -0600129 log_debug("dram_init() failed (err=%d)\n", ret);
Simon Glass030777d2017-01-16 07:03:56 -0700130 return ret;
131 }
Simon Glass3a1d96f2023-07-15 21:39:11 -0600132 log_debug("mrc\n");
Simon Glass7cf5fe02019-05-02 10:52:12 -0600133 if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
134 ret = mrccache_spl_save();
135 if (ret)
Simon Glass3a1d96f2023-07-15 21:39:11 -0600136 log_debug("Failed to write to mrccache (err=%d)\n",
137 ret);
Simon Glass7cf5fe02019-05-02 10:52:12 -0600138 }
139
Simon Glassdae11532020-04-30 21:21:42 -0600140#ifndef CONFIG_SYS_COREBOOT
Shiji Yangeff11fa2023-08-03 09:47:17 +0800141 debug("BSS clear from %lx to %lx len %lx\n", (ulong)__bss_start,
142 (ulong)__bss_end, (ulong)__bss_end - (ulong)__bss_start);
143 memset(__bss_start, 0, (ulong)__bss_end - (ulong)__bss_start);
Simon Glass47717592021-01-24 10:06:10 -0700144# ifndef CONFIG_TPL
Simon Glass030777d2017-01-16 07:03:56 -0700145
146 /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
147 ret = interrupt_init();
148 if (ret) {
149 debug("%s: interrupt_init() failed\n", __func__);
150 return ret;
151 }
152
153 /*
154 * The stack grows down from ptr. Put the global data at ptr. This
155 * will only be used for SPL. Once SPL loads U-Boot proper it will
156 * set up its own stack.
157 */
158 gd->new_gd = (struct global_data *)ptr;
159 memcpy(gd->new_gd, gd, sizeof(*gd));
Simon Glass23ae5c32023-07-15 21:39:05 -0600160
Simon Glass3a1d96f2023-07-15 21:39:11 -0600161 log_debug("logging\n");
Simon Glass23ae5c32023-07-15 21:39:05 -0600162 /*
163 * Make sure logging is disabled when we switch, since the log system
164 * list head will move
165 */
166 gd->new_gd->flags &= ~GD_FLG_LOG_READY;
Simon Glass030777d2017-01-16 07:03:56 -0700167 arch_setup_gd(gd->new_gd);
168 gd->start_addr_sp = (ulong)ptr;
169
Simon Glass23ae5c32023-07-15 21:39:05 -0600170 /* start up logging again, with the new list-head location */
171 ret = log_init();
172 if (ret) {
173 log_debug("Log setup failed (err=%d)\n", ret);
174 return ret;
175 }
176
Simon Glassfb842432023-07-15 21:38:36 -0600177 if (_LOG_DEBUG) {
178 ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
179 if (ret)
180 printf("mtrr_list failed\n");
181 }
182
Simon Glass030777d2017-01-16 07:03:56 -0700183 /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
184 ret = mtrr_add_request(MTRR_TYPE_WRBACK,
185 (1ULL << 32) - CONFIG_XIP_ROM_SIZE,
186 CONFIG_XIP_ROM_SIZE);
187 if (ret) {
Simon Glass7cf5fe02019-05-02 10:52:12 -0600188 debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
Simon Glass030777d2017-01-16 07:03:56 -0700189 return ret;
190 }
Simon Glassdae11532020-04-30 21:21:42 -0600191# else
Simon Glass0b3c5762019-10-20 21:37:49 -0600192 ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
193 if (ret)
194 debug("Could not find PUNIT (err=%d)\n", ret);
195
196 ret = set_max_freq();
197 if (ret)
198 debug("Failed to set CPU frequency (err=%d)\n", ret);
Simon Glassdae11532020-04-30 21:21:42 -0600199# endif
Simon Glass7cf5fe02019-05-02 10:52:12 -0600200#endif
Simon Glass3a1d96f2023-07-15 21:39:11 -0600201 log_debug("done\n");
Simon Glass030777d2017-01-16 07:03:56 -0700202
203 return 0;
204}
205
206void board_init_f(ulong flags)
207{
208 int ret;
209
210 ret = x86_spl_init();
211 if (ret) {
Simon Glassa0185fa2020-05-27 06:58:48 -0600212 printf("x86_spl_init: error %d\n", ret);
213 hang();
Simon Glass030777d2017-01-16 07:03:56 -0700214 }
Simon Glassdae11532020-04-30 21:21:42 -0600215#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
Simon Glass7cf5fe02019-05-02 10:52:12 -0600216 gd->bd = malloc(sizeof(*gd->bd));
217 if (!gd->bd) {
218 printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
219 hang();
220 }
221 board_init_r(gd, 0);
222#else
Simon Glass030777d2017-01-16 07:03:56 -0700223 /* Uninit CAR and jump to board_init_f_r() */
224 board_init_f_r_trampoline(gd->start_addr_sp);
Simon Glass7cf5fe02019-05-02 10:52:12 -0600225#endif
Simon Glass030777d2017-01-16 07:03:56 -0700226}
227
228void board_init_f_r(void)
229{
Simon Glass6e7b1b52023-05-04 16:50:57 -0600230 mtrr_commit(false);
231 init_cache();
Simon Glass030777d2017-01-16 07:03:56 -0700232 gd->flags &= ~GD_FLG_SERIAL_READY;
233 debug("cache status %d\n", dcache_status());
234 board_init_r(gd, 0);
235}
236
237u32 spl_boot_device(void)
238{
Simon Glass19da9c42019-09-25 08:11:39 -0600239 return BOOT_DEVICE_SPI_MMAP;
Simon Glass030777d2017-01-16 07:03:56 -0700240}
241
242int spl_start_uboot(void)
243{
244 return 0;
245}
246
247void spl_board_announce_boot_device(void)
248{
249 printf("SPI flash");
250}
251
252static int spl_board_load_image(struct spl_image_info *spl_image,
253 struct spl_boot_device *bootdev)
254{
255 spl_image->size = CONFIG_SYS_MONITOR_LEN;
Simon Glass72cc5382022-10-20 18:22:39 -0600256 spl_image->entry_point = CONFIG_TEXT_BASE;
257 spl_image->load_addr = CONFIG_TEXT_BASE;
Simon Glass030777d2017-01-16 07:03:56 -0700258 spl_image->os = IH_OS_U_BOOT;
259 spl_image->name = "U-Boot";
260
Simon Glass8c434342023-09-07 09:58:17 -0600261 if (spl_image->load_addr != spl_get_image_pos()) {
Simon Glass53ea0f62023-05-04 16:50:55 -0600262 /* Copy U-Boot from ROM */
263 memcpy((void *)spl_image->load_addr,
264 (void *)spl_get_image_pos(), spl_get_image_size());
Simon Glass91fcd1d2020-04-30 21:21:41 -0600265 }
266
Simon Glass030777d2017-01-16 07:03:56 -0700267 debug("Loading to %lx\n", spl_image->load_addr);
268
269 return 0;
270}
Simon Glass19da9c42019-09-25 08:11:39 -0600271SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
Simon Glass030777d2017-01-16 07:03:56 -0700272
273int spl_spi_load_image(void)
274{
275 return -EPERM;
276}
277
Simon Glass7cf5fe02019-05-02 10:52:12 -0600278#ifdef CONFIG_X86_RUN_64BIT
Simon Glass030777d2017-01-16 07:03:56 -0700279void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
280{
281 int ret;
282
283 printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
284 ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
285 debug("ret=%d\n", ret);
Simon Glass39c6f9b2019-09-25 08:11:38 -0600286 hang();
Simon Glass030777d2017-01-16 07:03:56 -0700287}
Simon Glass7cf5fe02019-05-02 10:52:12 -0600288#endif
289
290void spl_board_init(void)
291{
292#ifndef CONFIG_TPL
293 preloader_console_init();
294#endif
Simon Glass7dc0a452023-07-30 11:16:01 -0600295 if (IS_ENABLED(CONFIG_QEMU))
296 qemu_chipset_init();
Simon Glasse50c4552023-07-15 21:39:01 -0600297
298 if (CONFIG_IS_ENABLED(VIDEO)) {
299 struct udevice *dev;
300
301 /* Set up PCI video in SPL if required */
302 uclass_first_device_err(UCLASS_PCI, &dev);
303 uclass_first_device_err(UCLASS_VIDEO, &dev);
304 }
Simon Glass7cf5fe02019-05-02 10:52:12 -0600305}