Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2017 - All Rights Reserved |
| 4 | * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. |
| 5 | */ |
| 6 | #include <dt-bindings/pinctrl/stm32-pinfunc.h> |
| 7 | |
| 8 | &pinctrl { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 9 | adc1_in6_pins_a: adc1-in6-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 10 | pins { |
| 11 | pinmux = <STM32_PINMUX('F', 12, ANALOG)>; |
| 12 | }; |
| 13 | }; |
| 14 | |
| 15 | adc12_ain_pins_a: adc12-ain-0 { |
| 16 | pins { |
| 17 | pinmux = <STM32_PINMUX('C', 3, ANALOG)>, /* ADC1 in13 */ |
| 18 | <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ |
| 19 | <STM32_PINMUX('F', 13, ANALOG)>, /* ADC2 in2 */ |
| 20 | <STM32_PINMUX('F', 14, ANALOG)>; /* ADC2 in6 */ |
| 21 | }; |
| 22 | }; |
| 23 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 24 | adc12_ain_pins_b: adc12-ain-1 { |
| 25 | pins { |
| 26 | pinmux = <STM32_PINMUX('F', 12, ANALOG)>, /* ADC1 in6 */ |
| 27 | <STM32_PINMUX('F', 13, ANALOG)>; /* ADC2 in2 */ |
| 28 | }; |
| 29 | }; |
| 30 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 31 | adc12_usb_cc_pins_a: adc12-usb-cc-pins-0 { |
| 32 | pins { |
| 33 | pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* ADC12 in18 */ |
| 34 | <STM32_PINMUX('A', 5, ANALOG)>; /* ADC12 in19 */ |
| 35 | }; |
| 36 | }; |
| 37 | |
| 38 | cec_pins_a: cec-0 { |
| 39 | pins { |
| 40 | pinmux = <STM32_PINMUX('A', 15, AF4)>; |
| 41 | bias-disable; |
| 42 | drive-open-drain; |
| 43 | slew-rate = <0>; |
| 44 | }; |
| 45 | }; |
| 46 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 47 | cec_sleep_pins_a: cec-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 48 | pins { |
| 49 | pinmux = <STM32_PINMUX('A', 15, ANALOG)>; /* HDMI_CEC */ |
| 50 | }; |
| 51 | }; |
| 52 | |
| 53 | cec_pins_b: cec-1 { |
| 54 | pins { |
| 55 | pinmux = <STM32_PINMUX('B', 6, AF5)>; |
| 56 | bias-disable; |
| 57 | drive-open-drain; |
| 58 | slew-rate = <0>; |
| 59 | }; |
| 60 | }; |
| 61 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 62 | cec_sleep_pins_b: cec-sleep-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 63 | pins { |
| 64 | pinmux = <STM32_PINMUX('B', 6, ANALOG)>; /* HDMI_CEC */ |
| 65 | }; |
| 66 | }; |
| 67 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 68 | dac_ch1_pins_a: dac-ch1-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 69 | pins { |
| 70 | pinmux = <STM32_PINMUX('A', 4, ANALOG)>; |
| 71 | }; |
| 72 | }; |
| 73 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 74 | dac_ch2_pins_a: dac-ch2-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 75 | pins { |
| 76 | pinmux = <STM32_PINMUX('A', 5, ANALOG)>; |
| 77 | }; |
| 78 | }; |
| 79 | |
| 80 | dcmi_pins_a: dcmi-0 { |
| 81 | pins { |
| 82 | pinmux = <STM32_PINMUX('H', 8, AF13)>,/* DCMI_HSYNC */ |
| 83 | <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ |
| 84 | <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ |
| 85 | <STM32_PINMUX('H', 9, AF13)>,/* DCMI_D0 */ |
| 86 | <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ |
| 87 | <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ |
| 88 | <STM32_PINMUX('H', 12, AF13)>,/* DCMI_D3 */ |
| 89 | <STM32_PINMUX('H', 14, AF13)>,/* DCMI_D4 */ |
| 90 | <STM32_PINMUX('I', 4, AF13)>,/* DCMI_D5 */ |
| 91 | <STM32_PINMUX('B', 8, AF13)>,/* DCMI_D6 */ |
| 92 | <STM32_PINMUX('E', 6, AF13)>,/* DCMI_D7 */ |
| 93 | <STM32_PINMUX('I', 1, AF13)>,/* DCMI_D8 */ |
| 94 | <STM32_PINMUX('H', 7, AF13)>,/* DCMI_D9 */ |
| 95 | <STM32_PINMUX('I', 3, AF13)>,/* DCMI_D10 */ |
| 96 | <STM32_PINMUX('H', 15, AF13)>;/* DCMI_D11 */ |
| 97 | bias-disable; |
| 98 | }; |
| 99 | }; |
| 100 | |
| 101 | dcmi_sleep_pins_a: dcmi-sleep-0 { |
| 102 | pins { |
| 103 | pinmux = <STM32_PINMUX('H', 8, ANALOG)>,/* DCMI_HSYNC */ |
| 104 | <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ |
| 105 | <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ |
| 106 | <STM32_PINMUX('H', 9, ANALOG)>,/* DCMI_D0 */ |
| 107 | <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ |
| 108 | <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ |
| 109 | <STM32_PINMUX('H', 12, ANALOG)>,/* DCMI_D3 */ |
| 110 | <STM32_PINMUX('H', 14, ANALOG)>,/* DCMI_D4 */ |
| 111 | <STM32_PINMUX('I', 4, ANALOG)>,/* DCMI_D5 */ |
| 112 | <STM32_PINMUX('B', 8, ANALOG)>,/* DCMI_D6 */ |
| 113 | <STM32_PINMUX('E', 6, ANALOG)>,/* DCMI_D7 */ |
| 114 | <STM32_PINMUX('I', 1, ANALOG)>,/* DCMI_D8 */ |
| 115 | <STM32_PINMUX('H', 7, ANALOG)>,/* DCMI_D9 */ |
| 116 | <STM32_PINMUX('I', 3, ANALOG)>,/* DCMI_D10 */ |
| 117 | <STM32_PINMUX('H', 15, ANALOG)>;/* DCMI_D11 */ |
| 118 | }; |
| 119 | }; |
| 120 | |
Patrick Delaunay | b22fa9d | 2021-07-27 12:15:12 +0200 | [diff] [blame] | 121 | dcmi_pins_b: dcmi-1 { |
| 122 | pins { |
| 123 | pinmux = <STM32_PINMUX('A', 4, AF13)>,/* DCMI_HSYNC */ |
| 124 | <STM32_PINMUX('B', 7, AF13)>,/* DCMI_VSYNC */ |
| 125 | <STM32_PINMUX('A', 6, AF13)>,/* DCMI_PIXCLK */ |
| 126 | <STM32_PINMUX('C', 6, AF13)>,/* DCMI_D0 */ |
| 127 | <STM32_PINMUX('H', 10, AF13)>,/* DCMI_D1 */ |
| 128 | <STM32_PINMUX('H', 11, AF13)>,/* DCMI_D2 */ |
| 129 | <STM32_PINMUX('E', 1, AF13)>,/* DCMI_D3 */ |
| 130 | <STM32_PINMUX('E', 11, AF13)>,/* DCMI_D4 */ |
| 131 | <STM32_PINMUX('D', 3, AF13)>,/* DCMI_D5 */ |
| 132 | <STM32_PINMUX('E', 13, AF13)>,/* DCMI_D6 */ |
| 133 | <STM32_PINMUX('B', 9, AF13)>;/* DCMI_D7 */ |
| 134 | bias-disable; |
| 135 | }; |
| 136 | }; |
| 137 | |
| 138 | dcmi_sleep_pins_b: dcmi-sleep-1 { |
| 139 | pins { |
| 140 | pinmux = <STM32_PINMUX('A', 4, ANALOG)>,/* DCMI_HSYNC */ |
| 141 | <STM32_PINMUX('B', 7, ANALOG)>,/* DCMI_VSYNC */ |
| 142 | <STM32_PINMUX('A', 6, ANALOG)>,/* DCMI_PIXCLK */ |
| 143 | <STM32_PINMUX('C', 6, ANALOG)>,/* DCMI_D0 */ |
| 144 | <STM32_PINMUX('H', 10, ANALOG)>,/* DCMI_D1 */ |
| 145 | <STM32_PINMUX('H', 11, ANALOG)>,/* DCMI_D2 */ |
| 146 | <STM32_PINMUX('E', 1, ANALOG)>,/* DCMI_D3 */ |
| 147 | <STM32_PINMUX('E', 11, ANALOG)>,/* DCMI_D4 */ |
| 148 | <STM32_PINMUX('D', 3, ANALOG)>,/* DCMI_D5 */ |
| 149 | <STM32_PINMUX('E', 13, ANALOG)>,/* DCMI_D6 */ |
| 150 | <STM32_PINMUX('B', 9, ANALOG)>;/* DCMI_D7 */ |
| 151 | }; |
| 152 | }; |
| 153 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 154 | ethernet0_rgmii_pins_a: rgmii-0 { |
| 155 | pins1 { |
| 156 | pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ |
| 157 | <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ |
| 158 | <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ |
| 159 | <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ |
| 160 | <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ |
| 161 | <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ |
| 162 | <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ |
| 163 | <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ |
| 164 | bias-disable; |
| 165 | drive-push-pull; |
| 166 | slew-rate = <2>; |
| 167 | }; |
| 168 | pins2 { |
| 169 | pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ |
| 170 | bias-disable; |
| 171 | drive-push-pull; |
| 172 | slew-rate = <0>; |
| 173 | }; |
| 174 | pins3 { |
| 175 | pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ |
| 176 | <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ |
| 177 | <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */ |
| 178 | <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ |
| 179 | <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ |
| 180 | <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ |
| 181 | bias-disable; |
| 182 | }; |
| 183 | }; |
| 184 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 185 | ethernet0_rgmii_sleep_pins_a: rgmii-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 186 | pins1 { |
| 187 | pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ |
| 188 | <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ |
| 189 | <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ |
| 190 | <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ |
| 191 | <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ |
| 192 | <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ |
| 193 | <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ |
| 194 | <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ |
| 195 | <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ |
| 196 | <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ |
| 197 | <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| 198 | <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */ |
| 199 | <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ |
| 200 | <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ |
| 201 | <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ |
| 202 | }; |
| 203 | }; |
| 204 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 205 | ethernet0_rgmii_pins_b: rgmii-1 { |
| 206 | pins1 { |
| 207 | pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ |
| 208 | <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ |
| 209 | <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */ |
| 210 | <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ |
| 211 | <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ |
| 212 | <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ |
| 213 | <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */ |
| 214 | <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ |
| 215 | bias-disable; |
| 216 | drive-push-pull; |
| 217 | slew-rate = <2>; |
| 218 | }; |
| 219 | pins2 { |
| 220 | pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ |
| 221 | bias-disable; |
| 222 | drive-push-pull; |
| 223 | slew-rate = <0>; |
| 224 | }; |
| 225 | pins3 { |
| 226 | pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ |
| 227 | <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ |
| 228 | <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ |
| 229 | <STM32_PINMUX('H', 7, AF11)>, /* ETH_RGMII_RXD3 */ |
| 230 | <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ |
| 231 | <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ |
| 232 | bias-disable; |
| 233 | }; |
| 234 | }; |
| 235 | |
| 236 | ethernet0_rgmii_sleep_pins_b: rgmii-sleep-1 { |
| 237 | pins1 { |
| 238 | pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ |
| 239 | <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ |
| 240 | <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */ |
| 241 | <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ |
| 242 | <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ |
| 243 | <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ |
| 244 | <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ |
| 245 | <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ |
| 246 | <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ |
| 247 | <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ |
| 248 | <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| 249 | <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ |
| 250 | <STM32_PINMUX('H', 7, ANALOG)>, /* ETH_RGMII_RXD3 */ |
| 251 | <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ |
| 252 | <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ |
| 253 | }; |
| 254 | }; |
| 255 | |
Patrick Delaunay | 2b2d0b6 | 2020-07-06 13:26:51 +0200 | [diff] [blame] | 256 | ethernet0_rgmii_pins_c: rgmii-2 { |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 257 | pins1 { |
| 258 | pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */ |
| 259 | <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */ |
| 260 | <STM32_PINMUX('B', 12, AF11)>, /* ETH_RGMII_TXD0 */ |
| 261 | <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */ |
| 262 | <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */ |
| 263 | <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */ |
| 264 | <STM32_PINMUX('G', 11, AF11)>, /* ETH_RGMII_TX_CTL */ |
| 265 | <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */ |
| 266 | bias-disable; |
| 267 | drive-push-pull; |
| 268 | slew-rate = <2>; |
| 269 | }; |
| 270 | pins2 { |
| 271 | pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */ |
| 272 | bias-disable; |
| 273 | drive-push-pull; |
| 274 | slew-rate = <0>; |
| 275 | }; |
| 276 | pins3 { |
| 277 | pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */ |
| 278 | <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */ |
| 279 | <STM32_PINMUX('H', 6, AF11)>, /* ETH_RGMII_RXD2 */ |
| 280 | <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */ |
| 281 | <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */ |
| 282 | <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */ |
| 283 | bias-disable; |
| 284 | }; |
| 285 | }; |
| 286 | |
Patrick Delaunay | 2b2d0b6 | 2020-07-06 13:26:51 +0200 | [diff] [blame] | 287 | ethernet0_rgmii_sleep_pins_c: rgmii-sleep-2 { |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 288 | pins1 { |
| 289 | pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */ |
| 290 | <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */ |
| 291 | <STM32_PINMUX('B', 12, ANALOG)>, /* ETH_RGMII_TXD0 */ |
| 292 | <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */ |
| 293 | <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */ |
| 294 | <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */ |
| 295 | <STM32_PINMUX('G', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */ |
| 296 | <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */ |
| 297 | <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */ |
| 298 | <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */ |
| 299 | <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */ |
| 300 | <STM32_PINMUX('H', 6, ANALOG)>, /* ETH_RGMII_RXD2 */ |
| 301 | <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */ |
| 302 | <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */ |
| 303 | <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */ |
| 304 | }; |
| 305 | }; |
| 306 | |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 307 | ethernet0_rmii_pins_a: rmii-0 { |
| 308 | pins1 { |
| 309 | pinmux = <STM32_PINMUX('G', 13, AF11)>, /* ETH1_RMII_TXD0 */ |
| 310 | <STM32_PINMUX('G', 14, AF11)>, /* ETH1_RMII_TXD1 */ |
| 311 | <STM32_PINMUX('B', 11, AF11)>, /* ETH1_RMII_TX_EN */ |
| 312 | <STM32_PINMUX('A', 1, AF0)>, /* ETH1_RMII_REF_CLK */ |
| 313 | <STM32_PINMUX('A', 2, AF11)>, /* ETH1_MDIO */ |
| 314 | <STM32_PINMUX('C', 1, AF11)>; /* ETH1_MDC */ |
| 315 | bias-disable; |
| 316 | drive-push-pull; |
| 317 | slew-rate = <2>; |
| 318 | }; |
| 319 | pins2 { |
| 320 | pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RMII_RXD0 */ |
| 321 | <STM32_PINMUX('C', 5, AF11)>, /* ETH1_RMII_RXD1 */ |
| 322 | <STM32_PINMUX('A', 7, AF11)>; /* ETH1_RMII_CRS_DV */ |
| 323 | bias-disable; |
| 324 | }; |
| 325 | }; |
| 326 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 327 | ethernet0_rmii_sleep_pins_a: rmii-sleep-0 { |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 328 | pins1 { |
| 329 | pinmux = <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_RMII_TXD0 */ |
| 330 | <STM32_PINMUX('G', 14, ANALOG)>, /* ETH1_RMII_TXD1 */ |
| 331 | <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_RMII_TX_EN */ |
| 332 | <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ |
| 333 | <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ |
| 334 | <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RMII_RXD0 */ |
| 335 | <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RMII_RXD1 */ |
| 336 | <STM32_PINMUX('A', 1, ANALOG)>, /* ETH1_RMII_REF_CLK */ |
| 337 | <STM32_PINMUX('A', 7, ANALOG)>; /* ETH1_RMII_CRS_DV */ |
| 338 | }; |
| 339 | }; |
| 340 | |
Patrick Delaunay | 6f18219 | 2022-04-26 15:38:05 +0200 | [diff] [blame] | 341 | ethernet0_rmii_pins_b: rmii-1 { |
| 342 | pins1 { |
| 343 | pinmux = <STM32_PINMUX('B', 5, AF0)>, /* ETH1_CLK */ |
| 344 | <STM32_PINMUX('C', 1, AF11)>, /* ETH1_MDC */ |
| 345 | <STM32_PINMUX('G', 13, AF11)>, /* ETH1_TXD0 */ |
| 346 | <STM32_PINMUX('G', 14, AF11)>; /* ETH1_TXD1 */ |
| 347 | bias-disable; |
| 348 | drive-push-pull; |
| 349 | slew-rate = <1>; |
| 350 | }; |
| 351 | pins2 { |
| 352 | pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH1_MDIO */ |
| 353 | bias-disable; |
| 354 | drive-push-pull; |
| 355 | slew-rate = <0>; |
| 356 | }; |
| 357 | pins3 { |
| 358 | pinmux = <STM32_PINMUX('A', 7, AF11)>, /* ETH1_CRS_DV */ |
| 359 | <STM32_PINMUX('C', 4, AF11)>, /* ETH1_RXD0 */ |
| 360 | <STM32_PINMUX('C', 5, AF11)>; /* ETH1_RXD1 */ |
| 361 | bias-disable; |
| 362 | }; |
| 363 | pins4 { |
| 364 | pinmux = <STM32_PINMUX('B', 11, AF11)>; /* ETH1_TX_EN */ |
| 365 | }; |
| 366 | }; |
| 367 | |
| 368 | ethernet0_rmii_sleep_pins_b: rmii-sleep-1 { |
| 369 | pins1 { |
| 370 | pinmux = <STM32_PINMUX('A', 2, ANALOG)>, /* ETH1_MDIO */ |
| 371 | <STM32_PINMUX('A', 7, ANALOG)>, /* ETH1_CRS_DV */ |
| 372 | <STM32_PINMUX('B', 5, ANALOG)>, /* ETH1_CLK */ |
| 373 | <STM32_PINMUX('B', 11, ANALOG)>, /* ETH1_TX_EN */ |
| 374 | <STM32_PINMUX('C', 1, ANALOG)>, /* ETH1_MDC */ |
| 375 | <STM32_PINMUX('C', 4, ANALOG)>, /* ETH1_RXD0 */ |
| 376 | <STM32_PINMUX('C', 5, ANALOG)>, /* ETH1_RXD1 */ |
| 377 | <STM32_PINMUX('G', 13, ANALOG)>, /* ETH1_TXD0 */ |
| 378 | <STM32_PINMUX('G', 14, ANALOG)>; /* ETH1_TXD1 */ |
| 379 | }; |
| 380 | }; |
| 381 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 382 | fmc_pins_a: fmc-0 { |
| 383 | pins1 { |
| 384 | pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ |
| 385 | <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ |
| 386 | <STM32_PINMUX('D', 11, AF12)>, /* FMC_A16_FMC_CLE */ |
| 387 | <STM32_PINMUX('D', 12, AF12)>, /* FMC_A17_FMC_ALE */ |
| 388 | <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ |
| 389 | <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ |
| 390 | <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ |
| 391 | <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ |
| 392 | <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ |
| 393 | <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ |
| 394 | <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ |
| 395 | <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ |
| 396 | <STM32_PINMUX('G', 9, AF12)>; /* FMC_NE2_FMC_NCE */ |
| 397 | bias-disable; |
| 398 | drive-push-pull; |
| 399 | slew-rate = <1>; |
| 400 | }; |
| 401 | pins2 { |
| 402 | pinmux = <STM32_PINMUX('D', 6, AF12)>; /* FMC_NWAIT */ |
| 403 | bias-pull-up; |
| 404 | }; |
| 405 | }; |
| 406 | |
| 407 | fmc_sleep_pins_a: fmc-sleep-0 { |
| 408 | pins { |
| 409 | pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ |
| 410 | <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ |
| 411 | <STM32_PINMUX('D', 11, ANALOG)>, /* FMC_A16_FMC_CLE */ |
| 412 | <STM32_PINMUX('D', 12, ANALOG)>, /* FMC_A17_FMC_ALE */ |
| 413 | <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ |
| 414 | <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ |
| 415 | <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ |
| 416 | <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ |
| 417 | <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ |
| 418 | <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ |
| 419 | <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ |
| 420 | <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ |
| 421 | <STM32_PINMUX('D', 6, ANALOG)>, /* FMC_NWAIT */ |
| 422 | <STM32_PINMUX('G', 9, ANALOG)>; /* FMC_NE2_FMC_NCE */ |
| 423 | }; |
| 424 | }; |
| 425 | |
Patrick Delaunay | 6d39705 | 2021-01-11 12:33:36 +0100 | [diff] [blame] | 426 | fmc_pins_b: fmc-1 { |
| 427 | pins { |
| 428 | pinmux = <STM32_PINMUX('D', 4, AF12)>, /* FMC_NOE */ |
| 429 | <STM32_PINMUX('D', 5, AF12)>, /* FMC_NWE */ |
| 430 | <STM32_PINMUX('B', 7, AF12)>, /* FMC_NL */ |
| 431 | <STM32_PINMUX('D', 14, AF12)>, /* FMC_D0 */ |
| 432 | <STM32_PINMUX('D', 15, AF12)>, /* FMC_D1 */ |
| 433 | <STM32_PINMUX('D', 0, AF12)>, /* FMC_D2 */ |
| 434 | <STM32_PINMUX('D', 1, AF12)>, /* FMC_D3 */ |
| 435 | <STM32_PINMUX('E', 7, AF12)>, /* FMC_D4 */ |
| 436 | <STM32_PINMUX('E', 8, AF12)>, /* FMC_D5 */ |
| 437 | <STM32_PINMUX('E', 9, AF12)>, /* FMC_D6 */ |
| 438 | <STM32_PINMUX('E', 10, AF12)>, /* FMC_D7 */ |
| 439 | <STM32_PINMUX('E', 11, AF12)>, /* FMC_D8 */ |
| 440 | <STM32_PINMUX('E', 12, AF12)>, /* FMC_D9 */ |
| 441 | <STM32_PINMUX('E', 13, AF12)>, /* FMC_D10 */ |
| 442 | <STM32_PINMUX('E', 14, AF12)>, /* FMC_D11 */ |
| 443 | <STM32_PINMUX('E', 15, AF12)>, /* FMC_D12 */ |
| 444 | <STM32_PINMUX('D', 8, AF12)>, /* FMC_D13 */ |
| 445 | <STM32_PINMUX('D', 9, AF12)>, /* FMC_D14 */ |
| 446 | <STM32_PINMUX('D', 10, AF12)>, /* FMC_D15 */ |
| 447 | <STM32_PINMUX('G', 9, AF12)>, /* FMC_NE2_FMC_NCE */ |
| 448 | <STM32_PINMUX('G', 12, AF12)>; /* FMC_NE4 */ |
| 449 | bias-disable; |
| 450 | drive-push-pull; |
| 451 | slew-rate = <3>; |
| 452 | }; |
| 453 | }; |
| 454 | |
| 455 | fmc_sleep_pins_b: fmc-sleep-1 { |
| 456 | pins { |
| 457 | pinmux = <STM32_PINMUX('D', 4, ANALOG)>, /* FMC_NOE */ |
| 458 | <STM32_PINMUX('D', 5, ANALOG)>, /* FMC_NWE */ |
| 459 | <STM32_PINMUX('B', 7, ANALOG)>, /* FMC_NL */ |
| 460 | <STM32_PINMUX('D', 14, ANALOG)>, /* FMC_D0 */ |
| 461 | <STM32_PINMUX('D', 15, ANALOG)>, /* FMC_D1 */ |
| 462 | <STM32_PINMUX('D', 0, ANALOG)>, /* FMC_D2 */ |
| 463 | <STM32_PINMUX('D', 1, ANALOG)>, /* FMC_D3 */ |
| 464 | <STM32_PINMUX('E', 7, ANALOG)>, /* FMC_D4 */ |
| 465 | <STM32_PINMUX('E', 8, ANALOG)>, /* FMC_D5 */ |
| 466 | <STM32_PINMUX('E', 9, ANALOG)>, /* FMC_D6 */ |
| 467 | <STM32_PINMUX('E', 10, ANALOG)>, /* FMC_D7 */ |
| 468 | <STM32_PINMUX('E', 11, ANALOG)>, /* FMC_D8 */ |
| 469 | <STM32_PINMUX('E', 12, ANALOG)>, /* FMC_D9 */ |
| 470 | <STM32_PINMUX('E', 13, ANALOG)>, /* FMC_D10 */ |
| 471 | <STM32_PINMUX('E', 14, ANALOG)>, /* FMC_D11 */ |
| 472 | <STM32_PINMUX('E', 15, ANALOG)>, /* FMC_D12 */ |
| 473 | <STM32_PINMUX('D', 8, ANALOG)>, /* FMC_D13 */ |
| 474 | <STM32_PINMUX('D', 9, ANALOG)>, /* FMC_D14 */ |
| 475 | <STM32_PINMUX('D', 10, ANALOG)>, /* FMC_D15 */ |
| 476 | <STM32_PINMUX('G', 9, ANALOG)>, /* FMC_NE2_FMC_NCE */ |
| 477 | <STM32_PINMUX('G', 12, ANALOG)>; /* FMC_NE4 */ |
| 478 | }; |
| 479 | }; |
| 480 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 481 | i2c1_pins_a: i2c1-0 { |
| 482 | pins { |
| 483 | pinmux = <STM32_PINMUX('D', 12, AF5)>, /* I2C1_SCL */ |
| 484 | <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ |
| 485 | bias-disable; |
| 486 | drive-open-drain; |
| 487 | slew-rate = <0>; |
| 488 | }; |
| 489 | }; |
| 490 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 491 | i2c1_sleep_pins_a: i2c1-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 492 | pins { |
| 493 | pinmux = <STM32_PINMUX('D', 12, ANALOG)>, /* I2C1_SCL */ |
| 494 | <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ |
| 495 | }; |
| 496 | }; |
| 497 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 498 | i2c1_pins_b: i2c1-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 499 | pins { |
| 500 | pinmux = <STM32_PINMUX('F', 14, AF5)>, /* I2C1_SCL */ |
| 501 | <STM32_PINMUX('F', 15, AF5)>; /* I2C1_SDA */ |
| 502 | bias-disable; |
| 503 | drive-open-drain; |
| 504 | slew-rate = <0>; |
| 505 | }; |
| 506 | }; |
| 507 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 508 | i2c1_sleep_pins_b: i2c1-sleep-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 509 | pins { |
| 510 | pinmux = <STM32_PINMUX('F', 14, ANALOG)>, /* I2C1_SCL */ |
| 511 | <STM32_PINMUX('F', 15, ANALOG)>; /* I2C1_SDA */ |
| 512 | }; |
| 513 | }; |
| 514 | |
| 515 | i2c2_pins_a: i2c2-0 { |
| 516 | pins { |
| 517 | pinmux = <STM32_PINMUX('H', 4, AF4)>, /* I2C2_SCL */ |
| 518 | <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ |
| 519 | bias-disable; |
| 520 | drive-open-drain; |
| 521 | slew-rate = <0>; |
| 522 | }; |
| 523 | }; |
| 524 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 525 | i2c2_sleep_pins_a: i2c2-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 526 | pins { |
| 527 | pinmux = <STM32_PINMUX('H', 4, ANALOG)>, /* I2C2_SCL */ |
| 528 | <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ |
| 529 | }; |
| 530 | }; |
| 531 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 532 | i2c2_pins_b1: i2c2-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 533 | pins { |
| 534 | pinmux = <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ |
| 535 | bias-disable; |
| 536 | drive-open-drain; |
| 537 | slew-rate = <0>; |
| 538 | }; |
| 539 | }; |
| 540 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 541 | i2c2_sleep_pins_b1: i2c2-sleep-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 542 | pins { |
| 543 | pinmux = <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ |
| 544 | }; |
| 545 | }; |
| 546 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 547 | i2c2_pins_c: i2c2-2 { |
Marek Vasut | da77909 | 2020-05-26 04:30:21 +0200 | [diff] [blame] | 548 | pins { |
| 549 | pinmux = <STM32_PINMUX('F', 1, AF4)>, /* I2C2_SCL */ |
| 550 | <STM32_PINMUX('H', 5, AF4)>; /* I2C2_SDA */ |
| 551 | bias-disable; |
| 552 | drive-open-drain; |
| 553 | slew-rate = <0>; |
| 554 | }; |
| 555 | }; |
| 556 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 557 | i2c2_pins_sleep_c: i2c2-sleep-2 { |
Marek Vasut | da77909 | 2020-05-26 04:30:21 +0200 | [diff] [blame] | 558 | pins { |
| 559 | pinmux = <STM32_PINMUX('F', 1, ANALOG)>, /* I2C2_SCL */ |
| 560 | <STM32_PINMUX('H', 5, ANALOG)>; /* I2C2_SDA */ |
| 561 | }; |
| 562 | }; |
| 563 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 564 | i2c5_pins_a: i2c5-0 { |
| 565 | pins { |
| 566 | pinmux = <STM32_PINMUX('A', 11, AF4)>, /* I2C5_SCL */ |
| 567 | <STM32_PINMUX('A', 12, AF4)>; /* I2C5_SDA */ |
| 568 | bias-disable; |
| 569 | drive-open-drain; |
| 570 | slew-rate = <0>; |
| 571 | }; |
| 572 | }; |
| 573 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 574 | i2c5_sleep_pins_a: i2c5-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 575 | pins { |
| 576 | pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* I2C5_SCL */ |
| 577 | <STM32_PINMUX('A', 12, ANALOG)>; /* I2C5_SDA */ |
| 578 | |
| 579 | }; |
| 580 | }; |
| 581 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 582 | i2c5_pins_b: i2c5-1 { |
| 583 | pins { |
| 584 | pinmux = <STM32_PINMUX('D', 0, AF4)>, /* I2C5_SCL */ |
| 585 | <STM32_PINMUX('D', 1, AF4)>; /* I2C5_SDA */ |
| 586 | bias-disable; |
| 587 | drive-open-drain; |
| 588 | slew-rate = <0>; |
| 589 | }; |
| 590 | }; |
| 591 | |
| 592 | i2c5_sleep_pins_b: i2c5-sleep-1 { |
| 593 | pins { |
| 594 | pinmux = <STM32_PINMUX('D', 0, ANALOG)>, /* I2C5_SCL */ |
| 595 | <STM32_PINMUX('D', 1, ANALOG)>; /* I2C5_SDA */ |
| 596 | }; |
| 597 | }; |
| 598 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 599 | i2s2_pins_a: i2s2-0 { |
| 600 | pins { |
| 601 | pinmux = <STM32_PINMUX('I', 3, AF5)>, /* I2S2_SDO */ |
| 602 | <STM32_PINMUX('B', 9, AF5)>, /* I2S2_WS */ |
| 603 | <STM32_PINMUX('A', 9, AF5)>; /* I2S2_CK */ |
| 604 | slew-rate = <1>; |
| 605 | drive-push-pull; |
| 606 | bias-disable; |
| 607 | }; |
| 608 | }; |
| 609 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 610 | i2s2_sleep_pins_a: i2s2-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 611 | pins { |
| 612 | pinmux = <STM32_PINMUX('I', 3, ANALOG)>, /* I2S2_SDO */ |
| 613 | <STM32_PINMUX('B', 9, ANALOG)>, /* I2S2_WS */ |
| 614 | <STM32_PINMUX('A', 9, ANALOG)>; /* I2S2_CK */ |
| 615 | }; |
| 616 | }; |
| 617 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 618 | ltdc_pins_a: ltdc-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 619 | pins { |
| 620 | pinmux = <STM32_PINMUX('G', 7, AF14)>, /* LCD_CLK */ |
| 621 | <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ |
| 622 | <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ |
| 623 | <STM32_PINMUX('F', 10, AF14)>, /* LCD_DE */ |
| 624 | <STM32_PINMUX('H', 2, AF14)>, /* LCD_R0 */ |
| 625 | <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ |
| 626 | <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ |
| 627 | <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ |
| 628 | <STM32_PINMUX('H', 10, AF14)>, /* LCD_R4 */ |
| 629 | <STM32_PINMUX('C', 0, AF14)>, /* LCD_R5 */ |
| 630 | <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ |
| 631 | <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ |
| 632 | <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ |
| 633 | <STM32_PINMUX('E', 6, AF14)>, /* LCD_G1 */ |
| 634 | <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ |
| 635 | <STM32_PINMUX('H', 14, AF14)>, /* LCD_G3 */ |
| 636 | <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ |
| 637 | <STM32_PINMUX('I', 0, AF14)>, /* LCD_G5 */ |
| 638 | <STM32_PINMUX('I', 1, AF14)>, /* LCD_G6 */ |
| 639 | <STM32_PINMUX('I', 2, AF14)>, /* LCD_G7 */ |
| 640 | <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ |
| 641 | <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ |
| 642 | <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ |
| 643 | <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ |
| 644 | <STM32_PINMUX('I', 4, AF14)>, /* LCD_B4 */ |
| 645 | <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ |
| 646 | <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ |
| 647 | <STM32_PINMUX('D', 8, AF14)>; /* LCD_B7 */ |
| 648 | bias-disable; |
| 649 | drive-push-pull; |
| 650 | slew-rate = <1>; |
| 651 | }; |
| 652 | }; |
| 653 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 654 | ltdc_sleep_pins_a: ltdc-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 655 | pins { |
| 656 | pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ |
| 657 | <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ |
| 658 | <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ |
| 659 | <STM32_PINMUX('F', 10, ANALOG)>, /* LCD_DE */ |
| 660 | <STM32_PINMUX('H', 2, ANALOG)>, /* LCD_R0 */ |
| 661 | <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ |
| 662 | <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ |
| 663 | <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ |
| 664 | <STM32_PINMUX('H', 10, ANALOG)>, /* LCD_R4 */ |
| 665 | <STM32_PINMUX('C', 0, ANALOG)>, /* LCD_R5 */ |
| 666 | <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ |
| 667 | <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ |
| 668 | <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ |
| 669 | <STM32_PINMUX('E', 6, ANALOG)>, /* LCD_G1 */ |
| 670 | <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ |
| 671 | <STM32_PINMUX('H', 14, ANALOG)>, /* LCD_G3 */ |
| 672 | <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ |
| 673 | <STM32_PINMUX('I', 0, ANALOG)>, /* LCD_G5 */ |
| 674 | <STM32_PINMUX('I', 1, ANALOG)>, /* LCD_G6 */ |
| 675 | <STM32_PINMUX('I', 2, ANALOG)>, /* LCD_G7 */ |
| 676 | <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ |
| 677 | <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ |
| 678 | <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ |
| 679 | <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ |
| 680 | <STM32_PINMUX('I', 4, ANALOG)>, /* LCD_B4 */ |
| 681 | <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ |
| 682 | <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ |
| 683 | <STM32_PINMUX('D', 8, ANALOG)>; /* LCD_B7 */ |
| 684 | }; |
| 685 | }; |
| 686 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 687 | ltdc_pins_b: ltdc-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 688 | pins { |
| 689 | pinmux = <STM32_PINMUX('I', 14, AF14)>, /* LCD_CLK */ |
| 690 | <STM32_PINMUX('I', 12, AF14)>, /* LCD_HSYNC */ |
| 691 | <STM32_PINMUX('I', 13, AF14)>, /* LCD_VSYNC */ |
| 692 | <STM32_PINMUX('K', 7, AF14)>, /* LCD_DE */ |
| 693 | <STM32_PINMUX('I', 15, AF14)>, /* LCD_R0 */ |
| 694 | <STM32_PINMUX('J', 0, AF14)>, /* LCD_R1 */ |
| 695 | <STM32_PINMUX('J', 1, AF14)>, /* LCD_R2 */ |
| 696 | <STM32_PINMUX('J', 2, AF14)>, /* LCD_R3 */ |
| 697 | <STM32_PINMUX('J', 3, AF14)>, /* LCD_R4 */ |
| 698 | <STM32_PINMUX('J', 4, AF14)>, /* LCD_R5 */ |
| 699 | <STM32_PINMUX('J', 5, AF14)>, /* LCD_R6 */ |
| 700 | <STM32_PINMUX('J', 6, AF14)>, /* LCD_R7 */ |
| 701 | <STM32_PINMUX('J', 7, AF14)>, /* LCD_G0 */ |
| 702 | <STM32_PINMUX('J', 8, AF14)>, /* LCD_G1 */ |
| 703 | <STM32_PINMUX('J', 9, AF14)>, /* LCD_G2 */ |
| 704 | <STM32_PINMUX('J', 10, AF14)>, /* LCD_G3 */ |
| 705 | <STM32_PINMUX('J', 11, AF14)>, /* LCD_G4 */ |
| 706 | <STM32_PINMUX('K', 0, AF14)>, /* LCD_G5 */ |
| 707 | <STM32_PINMUX('K', 1, AF14)>, /* LCD_G6 */ |
| 708 | <STM32_PINMUX('K', 2, AF14)>, /* LCD_G7 */ |
| 709 | <STM32_PINMUX('J', 12, AF14)>, /* LCD_B0 */ |
| 710 | <STM32_PINMUX('J', 13, AF14)>, /* LCD_B1 */ |
| 711 | <STM32_PINMUX('J', 14, AF14)>, /* LCD_B2 */ |
| 712 | <STM32_PINMUX('J', 15, AF14)>, /* LCD_B3 */ |
| 713 | <STM32_PINMUX('K', 3, AF14)>, /* LCD_B4 */ |
| 714 | <STM32_PINMUX('K', 4, AF14)>, /* LCD_B5 */ |
| 715 | <STM32_PINMUX('K', 5, AF14)>, /* LCD_B6 */ |
| 716 | <STM32_PINMUX('K', 6, AF14)>; /* LCD_B7 */ |
| 717 | bias-disable; |
| 718 | drive-push-pull; |
| 719 | slew-rate = <1>; |
| 720 | }; |
| 721 | }; |
| 722 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 723 | ltdc_sleep_pins_b: ltdc-sleep-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 724 | pins { |
| 725 | pinmux = <STM32_PINMUX('I', 14, ANALOG)>, /* LCD_CLK */ |
| 726 | <STM32_PINMUX('I', 12, ANALOG)>, /* LCD_HSYNC */ |
| 727 | <STM32_PINMUX('I', 13, ANALOG)>, /* LCD_VSYNC */ |
| 728 | <STM32_PINMUX('K', 7, ANALOG)>, /* LCD_DE */ |
| 729 | <STM32_PINMUX('I', 15, ANALOG)>, /* LCD_R0 */ |
| 730 | <STM32_PINMUX('J', 0, ANALOG)>, /* LCD_R1 */ |
| 731 | <STM32_PINMUX('J', 1, ANALOG)>, /* LCD_R2 */ |
| 732 | <STM32_PINMUX('J', 2, ANALOG)>, /* LCD_R3 */ |
| 733 | <STM32_PINMUX('J', 3, ANALOG)>, /* LCD_R4 */ |
| 734 | <STM32_PINMUX('J', 4, ANALOG)>, /* LCD_R5 */ |
| 735 | <STM32_PINMUX('J', 5, ANALOG)>, /* LCD_R6 */ |
| 736 | <STM32_PINMUX('J', 6, ANALOG)>, /* LCD_R7 */ |
| 737 | <STM32_PINMUX('J', 7, ANALOG)>, /* LCD_G0 */ |
| 738 | <STM32_PINMUX('J', 8, ANALOG)>, /* LCD_G1 */ |
| 739 | <STM32_PINMUX('J', 9, ANALOG)>, /* LCD_G2 */ |
| 740 | <STM32_PINMUX('J', 10, ANALOG)>, /* LCD_G3 */ |
| 741 | <STM32_PINMUX('J', 11, ANALOG)>, /* LCD_G4 */ |
| 742 | <STM32_PINMUX('K', 0, ANALOG)>, /* LCD_G5 */ |
| 743 | <STM32_PINMUX('K', 1, ANALOG)>, /* LCD_G6 */ |
| 744 | <STM32_PINMUX('K', 2, ANALOG)>, /* LCD_G7 */ |
| 745 | <STM32_PINMUX('J', 12, ANALOG)>, /* LCD_B0 */ |
| 746 | <STM32_PINMUX('J', 13, ANALOG)>, /* LCD_B1 */ |
| 747 | <STM32_PINMUX('J', 14, ANALOG)>, /* LCD_B2 */ |
| 748 | <STM32_PINMUX('J', 15, ANALOG)>, /* LCD_B3 */ |
| 749 | <STM32_PINMUX('K', 3, ANALOG)>, /* LCD_B4 */ |
| 750 | <STM32_PINMUX('K', 4, ANALOG)>, /* LCD_B5 */ |
| 751 | <STM32_PINMUX('K', 5, ANALOG)>, /* LCD_B6 */ |
| 752 | <STM32_PINMUX('K', 6, ANALOG)>; /* LCD_B7 */ |
| 753 | }; |
| 754 | }; |
| 755 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 756 | ltdc_pins_c: ltdc-2 { |
| 757 | pins1 { |
| 758 | pinmux = <STM32_PINMUX('B', 1, AF9)>, /* LTDC_R6 */ |
| 759 | <STM32_PINMUX('B', 9, AF14)>, /* LTDC_B7 */ |
| 760 | <STM32_PINMUX('C', 0, AF14)>, /* LTDC_R5 */ |
| 761 | <STM32_PINMUX('D', 3, AF14)>, /* LTDC_G7 */ |
| 762 | <STM32_PINMUX('D', 6, AF14)>, /* LTDC_B2 */ |
| 763 | <STM32_PINMUX('D', 10, AF14)>, /* LTDC_B3 */ |
| 764 | <STM32_PINMUX('E', 11, AF14)>, /* LTDC_G3 */ |
| 765 | <STM32_PINMUX('E', 12, AF14)>, /* LTDC_B4 */ |
| 766 | <STM32_PINMUX('E', 13, AF14)>, /* LTDC_DE */ |
| 767 | <STM32_PINMUX('E', 15, AF14)>, /* LTDC_R7 */ |
| 768 | <STM32_PINMUX('H', 4, AF9)>, /* LTDC_G5 */ |
| 769 | <STM32_PINMUX('H', 8, AF14)>, /* LTDC_R2 */ |
| 770 | <STM32_PINMUX('H', 9, AF14)>, /* LTDC_R3 */ |
| 771 | <STM32_PINMUX('H', 10, AF14)>, /* LTDC_R4 */ |
| 772 | <STM32_PINMUX('H', 13, AF14)>, /* LTDC_G2 */ |
| 773 | <STM32_PINMUX('H', 15, AF14)>, /* LTDC_G4 */ |
| 774 | <STM32_PINMUX('I', 1, AF14)>, /* LTDC_G6 */ |
| 775 | <STM32_PINMUX('I', 5, AF14)>, /* LTDC_B5 */ |
| 776 | <STM32_PINMUX('I', 6, AF14)>, /* LTDC_B6 */ |
| 777 | <STM32_PINMUX('I', 9, AF14)>, /* LTDC_VSYNC */ |
| 778 | <STM32_PINMUX('I', 10, AF14)>; /* LTDC_HSYNC */ |
| 779 | bias-disable; |
| 780 | drive-push-pull; |
| 781 | slew-rate = <0>; |
| 782 | }; |
| 783 | pins2 { |
| 784 | pinmux = <STM32_PINMUX('E', 14, AF14)>; /* LTDC_CLK */ |
| 785 | bias-disable; |
| 786 | drive-push-pull; |
| 787 | slew-rate = <1>; |
| 788 | }; |
| 789 | }; |
| 790 | |
| 791 | ltdc_sleep_pins_c: ltdc-sleep-2 { |
| 792 | pins1 { |
| 793 | pinmux = <STM32_PINMUX('B', 1, ANALOG)>, /* LTDC_R6 */ |
| 794 | <STM32_PINMUX('B', 9, ANALOG)>, /* LTDC_B7 */ |
| 795 | <STM32_PINMUX('C', 0, ANALOG)>, /* LTDC_R5 */ |
| 796 | <STM32_PINMUX('D', 3, ANALOG)>, /* LTDC_G7 */ |
| 797 | <STM32_PINMUX('D', 6, ANALOG)>, /* LTDC_B2 */ |
| 798 | <STM32_PINMUX('D', 10, ANALOG)>, /* LTDC_B3 */ |
| 799 | <STM32_PINMUX('E', 11, ANALOG)>, /* LTDC_G3 */ |
| 800 | <STM32_PINMUX('E', 12, ANALOG)>, /* LTDC_B4 */ |
| 801 | <STM32_PINMUX('E', 13, ANALOG)>, /* LTDC_DE */ |
| 802 | <STM32_PINMUX('E', 15, ANALOG)>, /* LTDC_R7 */ |
| 803 | <STM32_PINMUX('H', 4, ANALOG)>, /* LTDC_G5 */ |
| 804 | <STM32_PINMUX('H', 8, ANALOG)>, /* LTDC_R2 */ |
| 805 | <STM32_PINMUX('H', 9, ANALOG)>, /* LTDC_R3 */ |
| 806 | <STM32_PINMUX('H', 10, ANALOG)>, /* LTDC_R4 */ |
| 807 | <STM32_PINMUX('H', 13, ANALOG)>, /* LTDC_G2 */ |
| 808 | <STM32_PINMUX('H', 15, ANALOG)>, /* LTDC_G4 */ |
| 809 | <STM32_PINMUX('I', 1, ANALOG)>, /* LTDC_G6 */ |
| 810 | <STM32_PINMUX('I', 5, ANALOG)>, /* LTDC_B5 */ |
| 811 | <STM32_PINMUX('I', 6, ANALOG)>, /* LTDC_B6 */ |
| 812 | <STM32_PINMUX('I', 9, ANALOG)>, /* LTDC_VSYNC */ |
| 813 | <STM32_PINMUX('I', 10, ANALOG)>, /* LTDC_HSYNC */ |
| 814 | <STM32_PINMUX('E', 14, ANALOG)>; /* LTDC_CLK */ |
| 815 | }; |
| 816 | }; |
| 817 | |
| 818 | ltdc_pins_d: ltdc-3 { |
| 819 | pins1 { |
| 820 | pinmux = <STM32_PINMUX('G', 7, AF14)>; /* LCD_CLK */ |
| 821 | bias-disable; |
| 822 | drive-push-pull; |
| 823 | slew-rate = <3>; |
| 824 | }; |
| 825 | pins2 { |
| 826 | pinmux = <STM32_PINMUX('I', 10, AF14)>, /* LCD_HSYNC */ |
| 827 | <STM32_PINMUX('I', 9, AF14)>, /* LCD_VSYNC */ |
| 828 | <STM32_PINMUX('E', 13, AF14)>, /* LCD_DE */ |
| 829 | <STM32_PINMUX('G', 13, AF14)>, /* LCD_R0 */ |
| 830 | <STM32_PINMUX('H', 3, AF14)>, /* LCD_R1 */ |
| 831 | <STM32_PINMUX('H', 8, AF14)>, /* LCD_R2 */ |
| 832 | <STM32_PINMUX('H', 9, AF14)>, /* LCD_R3 */ |
| 833 | <STM32_PINMUX('A', 5, AF14)>, /* LCD_R4 */ |
| 834 | <STM32_PINMUX('H', 11, AF14)>, /* LCD_R5 */ |
| 835 | <STM32_PINMUX('H', 12, AF14)>, /* LCD_R6 */ |
| 836 | <STM32_PINMUX('E', 15, AF14)>, /* LCD_R7 */ |
| 837 | <STM32_PINMUX('E', 5, AF14)>, /* LCD_G0 */ |
| 838 | <STM32_PINMUX('B', 0, AF14)>, /* LCD_G1 */ |
| 839 | <STM32_PINMUX('H', 13, AF14)>, /* LCD_G2 */ |
| 840 | <STM32_PINMUX('E', 11, AF14)>, /* LCD_G3 */ |
| 841 | <STM32_PINMUX('H', 15, AF14)>, /* LCD_G4 */ |
| 842 | <STM32_PINMUX('H', 4, AF9)>, /* LCD_G5 */ |
| 843 | <STM32_PINMUX('I', 11, AF9)>, /* LCD_G6 */ |
| 844 | <STM32_PINMUX('G', 8, AF14)>, /* LCD_G7 */ |
| 845 | <STM32_PINMUX('D', 9, AF14)>, /* LCD_B0 */ |
| 846 | <STM32_PINMUX('G', 12, AF14)>, /* LCD_B1 */ |
| 847 | <STM32_PINMUX('G', 10, AF14)>, /* LCD_B2 */ |
| 848 | <STM32_PINMUX('D', 10, AF14)>, /* LCD_B3 */ |
| 849 | <STM32_PINMUX('E', 12, AF14)>, /* LCD_B4 */ |
| 850 | <STM32_PINMUX('A', 3, AF14)>, /* LCD_B5 */ |
| 851 | <STM32_PINMUX('B', 8, AF14)>, /* LCD_B6 */ |
| 852 | <STM32_PINMUX('I', 7, AF14)>; /* LCD_B7 */ |
| 853 | bias-disable; |
| 854 | drive-push-pull; |
| 855 | slew-rate = <2>; |
| 856 | }; |
| 857 | }; |
| 858 | |
| 859 | ltdc_sleep_pins_d: ltdc-sleep-3 { |
| 860 | pins { |
| 861 | pinmux = <STM32_PINMUX('G', 7, ANALOG)>, /* LCD_CLK */ |
| 862 | <STM32_PINMUX('I', 10, ANALOG)>, /* LCD_HSYNC */ |
| 863 | <STM32_PINMUX('I', 9, ANALOG)>, /* LCD_VSYNC */ |
| 864 | <STM32_PINMUX('E', 13, ANALOG)>, /* LCD_DE */ |
| 865 | <STM32_PINMUX('G', 13, ANALOG)>, /* LCD_R0 */ |
| 866 | <STM32_PINMUX('H', 3, ANALOG)>, /* LCD_R1 */ |
| 867 | <STM32_PINMUX('H', 8, ANALOG)>, /* LCD_R2 */ |
| 868 | <STM32_PINMUX('H', 9, ANALOG)>, /* LCD_R3 */ |
| 869 | <STM32_PINMUX('A', 5, ANALOG)>, /* LCD_R4 */ |
| 870 | <STM32_PINMUX('H', 11, ANALOG)>, /* LCD_R5 */ |
| 871 | <STM32_PINMUX('H', 12, ANALOG)>, /* LCD_R6 */ |
| 872 | <STM32_PINMUX('E', 15, ANALOG)>, /* LCD_R7 */ |
| 873 | <STM32_PINMUX('E', 5, ANALOG)>, /* LCD_G0 */ |
| 874 | <STM32_PINMUX('B', 0, ANALOG)>, /* LCD_G1 */ |
| 875 | <STM32_PINMUX('H', 13, ANALOG)>, /* LCD_G2 */ |
| 876 | <STM32_PINMUX('E', 11, ANALOG)>, /* LCD_G3 */ |
| 877 | <STM32_PINMUX('H', 15, ANALOG)>, /* LCD_G4 */ |
| 878 | <STM32_PINMUX('H', 4, ANALOG)>, /* LCD_G5 */ |
| 879 | <STM32_PINMUX('I', 11, ANALOG)>, /* LCD_G6 */ |
| 880 | <STM32_PINMUX('G', 8, ANALOG)>, /* LCD_G7 */ |
| 881 | <STM32_PINMUX('D', 9, ANALOG)>, /* LCD_B0 */ |
| 882 | <STM32_PINMUX('G', 12, ANALOG)>, /* LCD_B1 */ |
| 883 | <STM32_PINMUX('G', 10, ANALOG)>, /* LCD_B2 */ |
| 884 | <STM32_PINMUX('D', 10, ANALOG)>, /* LCD_B3 */ |
| 885 | <STM32_PINMUX('E', 12, ANALOG)>, /* LCD_B4 */ |
| 886 | <STM32_PINMUX('A', 3, ANALOG)>, /* LCD_B5 */ |
| 887 | <STM32_PINMUX('B', 8, ANALOG)>, /* LCD_B6 */ |
| 888 | <STM32_PINMUX('I', 7, ANALOG)>; /* LCD_B7 */ |
| 889 | }; |
| 890 | }; |
| 891 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 892 | m_can1_pins_a: m-can1-0 { |
| 893 | pins1 { |
| 894 | pinmux = <STM32_PINMUX('H', 13, AF9)>; /* CAN1_TX */ |
| 895 | slew-rate = <1>; |
| 896 | drive-push-pull; |
| 897 | bias-disable; |
| 898 | }; |
| 899 | pins2 { |
| 900 | pinmux = <STM32_PINMUX('I', 9, AF9)>; /* CAN1_RX */ |
| 901 | bias-disable; |
| 902 | }; |
| 903 | }; |
| 904 | |
| 905 | m_can1_sleep_pins_a: m_can1-sleep-0 { |
| 906 | pins { |
| 907 | pinmux = <STM32_PINMUX('H', 13, ANALOG)>, /* CAN1_TX */ |
| 908 | <STM32_PINMUX('I', 9, ANALOG)>; /* CAN1_RX */ |
| 909 | }; |
| 910 | }; |
| 911 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 912 | m_can1_pins_b: m-can1-1 { |
| 913 | pins1 { |
| 914 | pinmux = <STM32_PINMUX('A', 12, AF9)>; /* CAN1_TX */ |
| 915 | slew-rate = <1>; |
| 916 | drive-push-pull; |
| 917 | bias-disable; |
| 918 | }; |
| 919 | pins2 { |
| 920 | pinmux = <STM32_PINMUX('A', 11, AF9)>; /* CAN1_RX */ |
| 921 | bias-disable; |
| 922 | }; |
| 923 | }; |
| 924 | |
| 925 | m_can1_sleep_pins_b: m_can1-sleep-1 { |
| 926 | pins { |
| 927 | pinmux = <STM32_PINMUX('A', 12, ANALOG)>, /* CAN1_TX */ |
| 928 | <STM32_PINMUX('A', 11, ANALOG)>; /* CAN1_RX */ |
| 929 | }; |
| 930 | }; |
| 931 | |
| 932 | m_can2_pins_a: m-can2-0 { |
| 933 | pins1 { |
| 934 | pinmux = <STM32_PINMUX('B', 13, AF9)>; /* CAN2_TX */ |
| 935 | slew-rate = <1>; |
| 936 | drive-push-pull; |
| 937 | bias-disable; |
| 938 | }; |
| 939 | pins2 { |
| 940 | pinmux = <STM32_PINMUX('B', 5, AF9)>; /* CAN2_RX */ |
| 941 | bias-disable; |
| 942 | }; |
| 943 | }; |
| 944 | |
| 945 | m_can2_sleep_pins_a: m_can2-sleep-0 { |
| 946 | pins { |
| 947 | pinmux = <STM32_PINMUX('B', 13, ANALOG)>, /* CAN2_TX */ |
| 948 | <STM32_PINMUX('B', 5, ANALOG)>; /* CAN2_RX */ |
| 949 | }; |
| 950 | }; |
| 951 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 952 | pwm1_pins_a: pwm1-0 { |
| 953 | pins { |
| 954 | pinmux = <STM32_PINMUX('E', 9, AF1)>, /* TIM1_CH1 */ |
| 955 | <STM32_PINMUX('E', 11, AF1)>, /* TIM1_CH2 */ |
| 956 | <STM32_PINMUX('E', 14, AF1)>; /* TIM1_CH4 */ |
| 957 | bias-pull-down; |
| 958 | drive-push-pull; |
| 959 | slew-rate = <0>; |
| 960 | }; |
| 961 | }; |
| 962 | |
| 963 | pwm1_sleep_pins_a: pwm1-sleep-0 { |
| 964 | pins { |
| 965 | pinmux = <STM32_PINMUX('E', 9, ANALOG)>, /* TIM1_CH1 */ |
| 966 | <STM32_PINMUX('E', 11, ANALOG)>, /* TIM1_CH2 */ |
| 967 | <STM32_PINMUX('E', 14, ANALOG)>; /* TIM1_CH4 */ |
| 968 | }; |
| 969 | }; |
| 970 | |
Patrick Delaunay | 6f18219 | 2022-04-26 15:38:05 +0200 | [diff] [blame] | 971 | pwm1_pins_b: pwm1-1 { |
| 972 | pins { |
| 973 | pinmux = <STM32_PINMUX('E', 9, AF1)>; /* TIM1_CH1 */ |
| 974 | bias-pull-down; |
| 975 | drive-push-pull; |
| 976 | slew-rate = <0>; |
| 977 | }; |
| 978 | }; |
| 979 | |
| 980 | pwm1_sleep_pins_b: pwm1-sleep-1 { |
| 981 | pins { |
| 982 | pinmux = <STM32_PINMUX('E', 9, ANALOG)>; /* TIM1_CH1 */ |
| 983 | }; |
| 984 | }; |
| 985 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 986 | pwm2_pins_a: pwm2-0 { |
| 987 | pins { |
| 988 | pinmux = <STM32_PINMUX('A', 3, AF1)>; /* TIM2_CH4 */ |
| 989 | bias-pull-down; |
| 990 | drive-push-pull; |
| 991 | slew-rate = <0>; |
| 992 | }; |
| 993 | }; |
| 994 | |
| 995 | pwm2_sleep_pins_a: pwm2-sleep-0 { |
| 996 | pins { |
| 997 | pinmux = <STM32_PINMUX('A', 3, ANALOG)>; /* TIM2_CH4 */ |
| 998 | }; |
| 999 | }; |
| 1000 | |
| 1001 | pwm3_pins_a: pwm3-0 { |
| 1002 | pins { |
| 1003 | pinmux = <STM32_PINMUX('C', 7, AF2)>; /* TIM3_CH2 */ |
| 1004 | bias-pull-down; |
| 1005 | drive-push-pull; |
| 1006 | slew-rate = <0>; |
| 1007 | }; |
| 1008 | }; |
| 1009 | |
| 1010 | pwm3_sleep_pins_a: pwm3-sleep-0 { |
| 1011 | pins { |
| 1012 | pinmux = <STM32_PINMUX('C', 7, ANALOG)>; /* TIM3_CH2 */ |
| 1013 | }; |
| 1014 | }; |
| 1015 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1016 | pwm3_pins_b: pwm3-1 { |
| 1017 | pins { |
| 1018 | pinmux = <STM32_PINMUX('B', 5, AF2)>; /* TIM3_CH2 */ |
| 1019 | bias-disable; |
| 1020 | drive-push-pull; |
| 1021 | slew-rate = <0>; |
| 1022 | }; |
| 1023 | }; |
| 1024 | |
| 1025 | pwm3_sleep_pins_b: pwm3-sleep-1 { |
| 1026 | pins { |
| 1027 | pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* TIM3_CH2 */ |
| 1028 | }; |
| 1029 | }; |
| 1030 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1031 | pwm4_pins_a: pwm4-0 { |
| 1032 | pins { |
| 1033 | pinmux = <STM32_PINMUX('D', 14, AF2)>, /* TIM4_CH3 */ |
| 1034 | <STM32_PINMUX('D', 15, AF2)>; /* TIM4_CH4 */ |
| 1035 | bias-pull-down; |
| 1036 | drive-push-pull; |
| 1037 | slew-rate = <0>; |
| 1038 | }; |
| 1039 | }; |
| 1040 | |
| 1041 | pwm4_sleep_pins_a: pwm4-sleep-0 { |
| 1042 | pins { |
| 1043 | pinmux = <STM32_PINMUX('D', 14, ANALOG)>, /* TIM4_CH3 */ |
| 1044 | <STM32_PINMUX('D', 15, ANALOG)>; /* TIM4_CH4 */ |
| 1045 | }; |
| 1046 | }; |
| 1047 | |
| 1048 | pwm4_pins_b: pwm4-1 { |
| 1049 | pins { |
| 1050 | pinmux = <STM32_PINMUX('D', 13, AF2)>; /* TIM4_CH2 */ |
| 1051 | bias-pull-down; |
| 1052 | drive-push-pull; |
| 1053 | slew-rate = <0>; |
| 1054 | }; |
| 1055 | }; |
| 1056 | |
| 1057 | pwm4_sleep_pins_b: pwm4-sleep-1 { |
| 1058 | pins { |
| 1059 | pinmux = <STM32_PINMUX('D', 13, ANALOG)>; /* TIM4_CH2 */ |
| 1060 | }; |
| 1061 | }; |
| 1062 | |
| 1063 | pwm5_pins_a: pwm5-0 { |
| 1064 | pins { |
| 1065 | pinmux = <STM32_PINMUX('H', 11, AF2)>; /* TIM5_CH2 */ |
| 1066 | bias-pull-down; |
| 1067 | drive-push-pull; |
| 1068 | slew-rate = <0>; |
| 1069 | }; |
| 1070 | }; |
| 1071 | |
| 1072 | pwm5_sleep_pins_a: pwm5-sleep-0 { |
| 1073 | pins { |
| 1074 | pinmux = <STM32_PINMUX('H', 11, ANALOG)>; /* TIM5_CH2 */ |
| 1075 | }; |
| 1076 | }; |
| 1077 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1078 | pwm5_pins_b: pwm5-1 { |
| 1079 | pins { |
| 1080 | pinmux = <STM32_PINMUX('H', 11, AF2)>, /* TIM5_CH2 */ |
| 1081 | <STM32_PINMUX('H', 12, AF2)>, /* TIM5_CH3 */ |
| 1082 | <STM32_PINMUX('I', 0, AF2)>; /* TIM5_CH4 */ |
| 1083 | bias-disable; |
| 1084 | drive-push-pull; |
| 1085 | slew-rate = <0>; |
| 1086 | }; |
| 1087 | }; |
| 1088 | |
| 1089 | pwm5_sleep_pins_b: pwm5-sleep-1 { |
| 1090 | pins { |
| 1091 | pinmux = <STM32_PINMUX('H', 11, ANALOG)>, /* TIM5_CH2 */ |
| 1092 | <STM32_PINMUX('H', 12, ANALOG)>, /* TIM5_CH3 */ |
| 1093 | <STM32_PINMUX('I', 0, ANALOG)>; /* TIM5_CH4 */ |
| 1094 | }; |
| 1095 | }; |
| 1096 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1097 | pwm8_pins_a: pwm8-0 { |
| 1098 | pins { |
| 1099 | pinmux = <STM32_PINMUX('I', 2, AF3)>; /* TIM8_CH4 */ |
| 1100 | bias-pull-down; |
| 1101 | drive-push-pull; |
| 1102 | slew-rate = <0>; |
| 1103 | }; |
| 1104 | }; |
| 1105 | |
| 1106 | pwm8_sleep_pins_a: pwm8-sleep-0 { |
| 1107 | pins { |
| 1108 | pinmux = <STM32_PINMUX('I', 2, ANALOG)>; /* TIM8_CH4 */ |
| 1109 | }; |
| 1110 | }; |
| 1111 | |
| 1112 | pwm12_pins_a: pwm12-0 { |
| 1113 | pins { |
| 1114 | pinmux = <STM32_PINMUX('H', 6, AF2)>; /* TIM12_CH1 */ |
| 1115 | bias-pull-down; |
| 1116 | drive-push-pull; |
| 1117 | slew-rate = <0>; |
| 1118 | }; |
| 1119 | }; |
| 1120 | |
| 1121 | pwm12_sleep_pins_a: pwm12-sleep-0 { |
| 1122 | pins { |
| 1123 | pinmux = <STM32_PINMUX('H', 6, ANALOG)>; /* TIM12_CH1 */ |
| 1124 | }; |
| 1125 | }; |
| 1126 | |
| 1127 | qspi_clk_pins_a: qspi-clk-0 { |
| 1128 | pins { |
| 1129 | pinmux = <STM32_PINMUX('F', 10, AF9)>; /* QSPI_CLK */ |
| 1130 | bias-disable; |
| 1131 | drive-push-pull; |
| 1132 | slew-rate = <3>; |
| 1133 | }; |
| 1134 | }; |
| 1135 | |
| 1136 | qspi_clk_sleep_pins_a: qspi-clk-sleep-0 { |
| 1137 | pins { |
| 1138 | pinmux = <STM32_PINMUX('F', 10, ANALOG)>; /* QSPI_CLK */ |
| 1139 | }; |
| 1140 | }; |
| 1141 | |
| 1142 | qspi_bk1_pins_a: qspi-bk1-0 { |
| 1143 | pins1 { |
| 1144 | pinmux = <STM32_PINMUX('F', 8, AF10)>, /* QSPI_BK1_IO0 */ |
| 1145 | <STM32_PINMUX('F', 9, AF10)>, /* QSPI_BK1_IO1 */ |
| 1146 | <STM32_PINMUX('F', 7, AF9)>, /* QSPI_BK1_IO2 */ |
| 1147 | <STM32_PINMUX('F', 6, AF9)>; /* QSPI_BK1_IO3 */ |
| 1148 | bias-disable; |
| 1149 | drive-push-pull; |
| 1150 | slew-rate = <1>; |
| 1151 | }; |
| 1152 | pins2 { |
| 1153 | pinmux = <STM32_PINMUX('B', 6, AF10)>; /* QSPI_BK1_NCS */ |
| 1154 | bias-pull-up; |
| 1155 | drive-push-pull; |
| 1156 | slew-rate = <1>; |
| 1157 | }; |
| 1158 | }; |
| 1159 | |
| 1160 | qspi_bk1_sleep_pins_a: qspi-bk1-sleep-0 { |
| 1161 | pins { |
| 1162 | pinmux = <STM32_PINMUX('F', 8, ANALOG)>, /* QSPI_BK1_IO0 */ |
| 1163 | <STM32_PINMUX('F', 9, ANALOG)>, /* QSPI_BK1_IO1 */ |
| 1164 | <STM32_PINMUX('F', 7, ANALOG)>, /* QSPI_BK1_IO2 */ |
| 1165 | <STM32_PINMUX('F', 6, ANALOG)>, /* QSPI_BK1_IO3 */ |
| 1166 | <STM32_PINMUX('B', 6, ANALOG)>; /* QSPI_BK1_NCS */ |
| 1167 | }; |
| 1168 | }; |
| 1169 | |
| 1170 | qspi_bk2_pins_a: qspi-bk2-0 { |
| 1171 | pins1 { |
| 1172 | pinmux = <STM32_PINMUX('H', 2, AF9)>, /* QSPI_BK2_IO0 */ |
| 1173 | <STM32_PINMUX('H', 3, AF9)>, /* QSPI_BK2_IO1 */ |
| 1174 | <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */ |
| 1175 | <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */ |
| 1176 | bias-disable; |
| 1177 | drive-push-pull; |
| 1178 | slew-rate = <1>; |
| 1179 | }; |
| 1180 | pins2 { |
| 1181 | pinmux = <STM32_PINMUX('C', 0, AF10)>; /* QSPI_BK2_NCS */ |
| 1182 | bias-pull-up; |
| 1183 | drive-push-pull; |
| 1184 | slew-rate = <1>; |
| 1185 | }; |
| 1186 | }; |
| 1187 | |
| 1188 | qspi_bk2_sleep_pins_a: qspi-bk2-sleep-0 { |
| 1189 | pins { |
| 1190 | pinmux = <STM32_PINMUX('H', 2, ANALOG)>, /* QSPI_BK2_IO0 */ |
| 1191 | <STM32_PINMUX('H', 3, ANALOG)>, /* QSPI_BK2_IO1 */ |
| 1192 | <STM32_PINMUX('G', 10, ANALOG)>, /* QSPI_BK2_IO2 */ |
| 1193 | <STM32_PINMUX('G', 7, ANALOG)>, /* QSPI_BK2_IO3 */ |
| 1194 | <STM32_PINMUX('C', 0, ANALOG)>; /* QSPI_BK2_NCS */ |
| 1195 | }; |
| 1196 | }; |
| 1197 | |
| 1198 | sai2a_pins_a: sai2a-0 { |
| 1199 | pins { |
| 1200 | pinmux = <STM32_PINMUX('I', 5, AF10)>, /* SAI2_SCK_A */ |
| 1201 | <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ |
| 1202 | <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ |
| 1203 | <STM32_PINMUX('E', 0, AF10)>; /* SAI2_MCLK_A */ |
| 1204 | slew-rate = <0>; |
| 1205 | drive-push-pull; |
| 1206 | bias-disable; |
| 1207 | }; |
| 1208 | }; |
| 1209 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1210 | sai2a_sleep_pins_a: sai2a-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1211 | pins { |
| 1212 | pinmux = <STM32_PINMUX('I', 5, ANALOG)>, /* SAI2_SCK_A */ |
| 1213 | <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ |
| 1214 | <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ |
| 1215 | <STM32_PINMUX('E', 0, ANALOG)>; /* SAI2_MCLK_A */ |
| 1216 | }; |
| 1217 | }; |
| 1218 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1219 | sai2a_pins_b: sai2a-1 { |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 1220 | pins1 { |
| 1221 | pinmux = <STM32_PINMUX('I', 6, AF10)>, /* SAI2_SD_A */ |
| 1222 | <STM32_PINMUX('I', 7, AF10)>, /* SAI2_FS_A */ |
| 1223 | <STM32_PINMUX('D', 13, AF10)>; /* SAI2_SCK_A */ |
| 1224 | slew-rate = <0>; |
| 1225 | drive-push-pull; |
| 1226 | bias-disable; |
| 1227 | }; |
| 1228 | }; |
| 1229 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1230 | sai2a_sleep_pins_b: sai2a-sleep-1 { |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 1231 | pins { |
| 1232 | pinmux = <STM32_PINMUX('I', 6, ANALOG)>, /* SAI2_SD_A */ |
| 1233 | <STM32_PINMUX('I', 7, ANALOG)>, /* SAI2_FS_A */ |
| 1234 | <STM32_PINMUX('D', 13, ANALOG)>; /* SAI2_SCK_A */ |
| 1235 | }; |
| 1236 | }; |
| 1237 | |
Patrick Delaunay | 37868aa | 2021-12-17 16:30:22 +0100 | [diff] [blame] | 1238 | sai2a_pins_c: sai2a-2 { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1239 | pins { |
| 1240 | pinmux = <STM32_PINMUX('D', 13, AF10)>, /* SAI2_SCK_A */ |
| 1241 | <STM32_PINMUX('D', 11, AF10)>, /* SAI2_SD_A */ |
| 1242 | <STM32_PINMUX('D', 12, AF10)>; /* SAI2_FS_A */ |
| 1243 | slew-rate = <0>; |
| 1244 | drive-push-pull; |
| 1245 | bias-disable; |
| 1246 | }; |
| 1247 | }; |
| 1248 | |
Patrick Delaunay | 37868aa | 2021-12-17 16:30:22 +0100 | [diff] [blame] | 1249 | sai2a_sleep_pins_c: sai2a-sleep-2 { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1250 | pins { |
| 1251 | pinmux = <STM32_PINMUX('D', 13, ANALOG)>, /* SAI2_SCK_A */ |
| 1252 | <STM32_PINMUX('D', 11, ANALOG)>, /* SAI2_SD_A */ |
| 1253 | <STM32_PINMUX('D', 12, ANALOG)>; /* SAI2_FS_A */ |
| 1254 | }; |
| 1255 | }; |
| 1256 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1257 | sai2b_pins_a: sai2b-0 { |
| 1258 | pins1 { |
| 1259 | pinmux = <STM32_PINMUX('E', 12, AF10)>, /* SAI2_SCK_B */ |
| 1260 | <STM32_PINMUX('E', 13, AF10)>, /* SAI2_FS_B */ |
| 1261 | <STM32_PINMUX('E', 14, AF10)>; /* SAI2_MCLK_B */ |
| 1262 | slew-rate = <0>; |
| 1263 | drive-push-pull; |
| 1264 | bias-disable; |
| 1265 | }; |
| 1266 | pins2 { |
| 1267 | pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ |
| 1268 | bias-disable; |
| 1269 | }; |
| 1270 | }; |
| 1271 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1272 | sai2b_sleep_pins_a: sai2b-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1273 | pins { |
| 1274 | pinmux = <STM32_PINMUX('F', 11, ANALOG)>, /* SAI2_SD_B */ |
| 1275 | <STM32_PINMUX('E', 12, ANALOG)>, /* SAI2_SCK_B */ |
| 1276 | <STM32_PINMUX('E', 13, ANALOG)>, /* SAI2_FS_B */ |
| 1277 | <STM32_PINMUX('E', 14, ANALOG)>; /* SAI2_MCLK_B */ |
| 1278 | }; |
| 1279 | }; |
| 1280 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1281 | sai2b_pins_b: sai2b-1 { |
| 1282 | pins { |
| 1283 | pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ |
| 1284 | bias-disable; |
| 1285 | }; |
| 1286 | }; |
| 1287 | |
| 1288 | sai2b_sleep_pins_b: sai2b-sleep-1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1289 | pins { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1290 | pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ |
| 1291 | }; |
| 1292 | }; |
| 1293 | |
Patrick Delaunay | 37868aa | 2021-12-17 16:30:22 +0100 | [diff] [blame] | 1294 | sai2b_pins_c: sai2b-2 { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1295 | pins1 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1296 | pinmux = <STM32_PINMUX('F', 11, AF10)>; /* SAI2_SD_B */ |
| 1297 | bias-disable; |
| 1298 | }; |
| 1299 | }; |
| 1300 | |
Patrick Delaunay | 37868aa | 2021-12-17 16:30:22 +0100 | [diff] [blame] | 1301 | sai2b_sleep_pins_c: sai2b-sleep-2 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1302 | pins { |
| 1303 | pinmux = <STM32_PINMUX('F', 11, ANALOG)>; /* SAI2_SD_B */ |
| 1304 | }; |
| 1305 | }; |
| 1306 | |
| 1307 | sai4a_pins_a: sai4a-0 { |
| 1308 | pins { |
| 1309 | pinmux = <STM32_PINMUX('B', 5, AF10)>; /* SAI4_SD_A */ |
| 1310 | slew-rate = <0>; |
| 1311 | drive-push-pull; |
| 1312 | bias-disable; |
| 1313 | }; |
| 1314 | }; |
| 1315 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1316 | sai4a_sleep_pins_a: sai4a-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1317 | pins { |
| 1318 | pinmux = <STM32_PINMUX('B', 5, ANALOG)>; /* SAI4_SD_A */ |
| 1319 | }; |
| 1320 | }; |
| 1321 | |
| 1322 | sdmmc1_b4_pins_a: sdmmc1-b4-0 { |
| 1323 | pins1 { |
| 1324 | pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
| 1325 | <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
| 1326 | <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
| 1327 | <STM32_PINMUX('C', 11, AF12)>, /* SDMMC1_D3 */ |
| 1328 | <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ |
| 1329 | slew-rate = <1>; |
| 1330 | drive-push-pull; |
| 1331 | bias-disable; |
| 1332 | }; |
| 1333 | pins2 { |
| 1334 | pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ |
| 1335 | slew-rate = <2>; |
| 1336 | drive-push-pull; |
| 1337 | bias-disable; |
| 1338 | }; |
| 1339 | }; |
| 1340 | |
| 1341 | sdmmc1_b4_od_pins_a: sdmmc1-b4-od-0 { |
| 1342 | pins1 { |
| 1343 | pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
| 1344 | <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
| 1345 | <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
| 1346 | <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ |
| 1347 | slew-rate = <1>; |
| 1348 | drive-push-pull; |
| 1349 | bias-disable; |
| 1350 | }; |
| 1351 | pins2 { |
| 1352 | pinmux = <STM32_PINMUX('C', 12, AF12)>; /* SDMMC1_CK */ |
| 1353 | slew-rate = <2>; |
| 1354 | drive-push-pull; |
| 1355 | bias-disable; |
| 1356 | }; |
| 1357 | pins3 { |
| 1358 | pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDMMC1_CMD */ |
| 1359 | slew-rate = <1>; |
| 1360 | drive-open-drain; |
| 1361 | bias-disable; |
| 1362 | }; |
| 1363 | }; |
| 1364 | |
Patrick Delaunay | e48a0d4 | 2021-06-29 12:01:07 +0200 | [diff] [blame] | 1365 | sdmmc1_b4_init_pins_a: sdmmc1-b4-init-0 { |
| 1366 | pins1 { |
| 1367 | pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDMMC1_D0 */ |
| 1368 | <STM32_PINMUX('C', 9, AF12)>, /* SDMMC1_D1 */ |
| 1369 | <STM32_PINMUX('C', 10, AF12)>, /* SDMMC1_D2 */ |
| 1370 | <STM32_PINMUX('C', 11, AF12)>; /* SDMMC1_D3 */ |
| 1371 | slew-rate = <1>; |
| 1372 | drive-push-pull; |
| 1373 | bias-disable; |
| 1374 | }; |
| 1375 | }; |
| 1376 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1377 | sdmmc1_b4_sleep_pins_a: sdmmc1-b4-sleep-0 { |
| 1378 | pins { |
| 1379 | pinmux = <STM32_PINMUX('C', 8, ANALOG)>, /* SDMMC1_D0 */ |
| 1380 | <STM32_PINMUX('C', 9, ANALOG)>, /* SDMMC1_D1 */ |
| 1381 | <STM32_PINMUX('C', 10, ANALOG)>, /* SDMMC1_D2 */ |
| 1382 | <STM32_PINMUX('C', 11, ANALOG)>, /* SDMMC1_D3 */ |
| 1383 | <STM32_PINMUX('C', 12, ANALOG)>, /* SDMMC1_CK */ |
| 1384 | <STM32_PINMUX('D', 2, ANALOG)>; /* SDMMC1_CMD */ |
| 1385 | }; |
| 1386 | }; |
| 1387 | |
| 1388 | sdmmc1_dir_pins_a: sdmmc1-dir-0 { |
| 1389 | pins1 { |
| 1390 | pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ |
| 1391 | <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ |
| 1392 | <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ |
| 1393 | slew-rate = <1>; |
| 1394 | drive-push-pull; |
| 1395 | bias-pull-up; |
| 1396 | }; |
| 1397 | pins2{ |
| 1398 | pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ |
| 1399 | bias-pull-up; |
| 1400 | }; |
| 1401 | }; |
| 1402 | |
Patrick Delaunay | e48a0d4 | 2021-06-29 12:01:07 +0200 | [diff] [blame] | 1403 | sdmmc1_dir_init_pins_a: sdmmc1-dir-init-0 { |
| 1404 | pins1 { |
| 1405 | pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ |
| 1406 | <STM32_PINMUX('C', 7, AF8)>, /* SDMMC1_D123DIR */ |
| 1407 | <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ |
| 1408 | slew-rate = <1>; |
| 1409 | drive-push-pull; |
| 1410 | bias-pull-up; |
| 1411 | }; |
| 1412 | }; |
| 1413 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1414 | sdmmc1_dir_sleep_pins_a: sdmmc1-dir-sleep-0 { |
| 1415 | pins { |
| 1416 | pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ |
| 1417 | <STM32_PINMUX('C', 7, ANALOG)>, /* SDMMC1_D123DIR */ |
| 1418 | <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ |
| 1419 | <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ |
| 1420 | }; |
| 1421 | }; |
| 1422 | |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 1423 | sdmmc1_dir_pins_b: sdmmc1-dir-1 { |
| 1424 | pins1 { |
| 1425 | pinmux = <STM32_PINMUX('F', 2, AF11)>, /* SDMMC1_D0DIR */ |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1426 | <STM32_PINMUX('E', 14, AF11)>, /* SDMMC1_D123DIR */ |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 1427 | <STM32_PINMUX('B', 9, AF11)>; /* SDMMC1_CDIR */ |
| 1428 | slew-rate = <1>; |
| 1429 | drive-push-pull; |
| 1430 | bias-pull-up; |
| 1431 | }; |
| 1432 | pins2{ |
| 1433 | pinmux = <STM32_PINMUX('E', 4, AF8)>; /* SDMMC1_CKIN */ |
| 1434 | bias-pull-up; |
| 1435 | }; |
| 1436 | }; |
| 1437 | |
| 1438 | sdmmc1_dir_sleep_pins_b: sdmmc1-dir-sleep-1 { |
| 1439 | pins { |
| 1440 | pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* SDMMC1_D0DIR */ |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1441 | <STM32_PINMUX('E', 14, ANALOG)>, /* SDMMC1_D123DIR */ |
| 1442 | <STM32_PINMUX('B', 9, ANALOG)>, /* SDMMC1_CDIR */ |
| 1443 | <STM32_PINMUX('E', 4, ANALOG)>; /* SDMMC1_CKIN */ |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 1444 | }; |
| 1445 | }; |
| 1446 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1447 | sdmmc2_b4_pins_a: sdmmc2-b4-0 { |
| 1448 | pins1 { |
| 1449 | pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ |
| 1450 | <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ |
| 1451 | <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ |
| 1452 | <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ |
| 1453 | <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
| 1454 | slew-rate = <1>; |
| 1455 | drive-push-pull; |
| 1456 | bias-pull-up; |
| 1457 | }; |
| 1458 | pins2 { |
| 1459 | pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ |
| 1460 | slew-rate = <2>; |
| 1461 | drive-push-pull; |
| 1462 | bias-pull-up; |
| 1463 | }; |
| 1464 | }; |
| 1465 | |
| 1466 | sdmmc2_b4_od_pins_a: sdmmc2-b4-od-0 { |
| 1467 | pins1 { |
| 1468 | pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ |
| 1469 | <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ |
| 1470 | <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ |
| 1471 | <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ |
| 1472 | slew-rate = <1>; |
| 1473 | drive-push-pull; |
| 1474 | bias-pull-up; |
| 1475 | }; |
| 1476 | pins2 { |
| 1477 | pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ |
| 1478 | slew-rate = <2>; |
| 1479 | drive-push-pull; |
| 1480 | bias-pull-up; |
| 1481 | }; |
| 1482 | pins3 { |
| 1483 | pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
| 1484 | slew-rate = <1>; |
| 1485 | drive-open-drain; |
| 1486 | bias-pull-up; |
| 1487 | }; |
| 1488 | }; |
| 1489 | |
| 1490 | sdmmc2_b4_sleep_pins_a: sdmmc2-b4-sleep-0 { |
| 1491 | pins { |
| 1492 | pinmux = <STM32_PINMUX('B', 14, ANALOG)>, /* SDMMC2_D0 */ |
| 1493 | <STM32_PINMUX('B', 15, ANALOG)>, /* SDMMC2_D1 */ |
| 1494 | <STM32_PINMUX('B', 3, ANALOG)>, /* SDMMC2_D2 */ |
| 1495 | <STM32_PINMUX('B', 4, ANALOG)>, /* SDMMC2_D3 */ |
| 1496 | <STM32_PINMUX('E', 3, ANALOG)>, /* SDMMC2_CK */ |
| 1497 | <STM32_PINMUX('G', 6, ANALOG)>; /* SDMMC2_CMD */ |
| 1498 | }; |
| 1499 | }; |
| 1500 | |
| 1501 | sdmmc2_b4_pins_b: sdmmc2-b4-1 { |
| 1502 | pins1 { |
| 1503 | pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ |
| 1504 | <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ |
| 1505 | <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ |
| 1506 | <STM32_PINMUX('B', 4, AF9)>, /* SDMMC2_D3 */ |
| 1507 | <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
| 1508 | slew-rate = <1>; |
| 1509 | drive-push-pull; |
| 1510 | bias-disable; |
| 1511 | }; |
| 1512 | pins2 { |
| 1513 | pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ |
| 1514 | slew-rate = <2>; |
| 1515 | drive-push-pull; |
| 1516 | bias-disable; |
| 1517 | }; |
| 1518 | }; |
| 1519 | |
| 1520 | sdmmc2_b4_od_pins_b: sdmmc2-b4-od-1 { |
| 1521 | pins1 { |
| 1522 | pinmux = <STM32_PINMUX('B', 14, AF9)>, /* SDMMC2_D0 */ |
| 1523 | <STM32_PINMUX('B', 15, AF9)>, /* SDMMC2_D1 */ |
| 1524 | <STM32_PINMUX('B', 3, AF9)>, /* SDMMC2_D2 */ |
| 1525 | <STM32_PINMUX('B', 4, AF9)>; /* SDMMC2_D3 */ |
| 1526 | slew-rate = <1>; |
| 1527 | drive-push-pull; |
| 1528 | bias-disable; |
| 1529 | }; |
| 1530 | pins2 { |
| 1531 | pinmux = <STM32_PINMUX('E', 3, AF9)>; /* SDMMC2_CK */ |
| 1532 | slew-rate = <2>; |
| 1533 | drive-push-pull; |
| 1534 | bias-disable; |
| 1535 | }; |
| 1536 | pins3 { |
| 1537 | pinmux = <STM32_PINMUX('G', 6, AF10)>; /* SDMMC2_CMD */ |
| 1538 | slew-rate = <1>; |
| 1539 | drive-open-drain; |
| 1540 | bias-disable; |
| 1541 | }; |
| 1542 | }; |
| 1543 | |
| 1544 | sdmmc2_d47_pins_a: sdmmc2-d47-0 { |
| 1545 | pins { |
| 1546 | pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ |
| 1547 | <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ |
| 1548 | <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ |
| 1549 | <STM32_PINMUX('D', 3, AF9)>; /* SDMMC2_D7 */ |
| 1550 | slew-rate = <1>; |
| 1551 | drive-push-pull; |
| 1552 | bias-pull-up; |
| 1553 | }; |
| 1554 | }; |
| 1555 | |
| 1556 | sdmmc2_d47_sleep_pins_a: sdmmc2-d47-sleep-0 { |
| 1557 | pins { |
| 1558 | pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ |
| 1559 | <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ |
| 1560 | <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ |
| 1561 | <STM32_PINMUX('D', 3, ANALOG)>; /* SDMMC2_D7 */ |
| 1562 | }; |
| 1563 | }; |
| 1564 | |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 1565 | sdmmc2_d47_pins_b: sdmmc2-d47-1 { |
| 1566 | pins { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1567 | pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ |
| 1568 | <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ |
| 1569 | <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ |
| 1570 | <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ |
| 1571 | slew-rate = <1>; |
| 1572 | drive-push-pull; |
| 1573 | bias-disable; |
| 1574 | }; |
| 1575 | }; |
| 1576 | |
| 1577 | sdmmc2_d47_sleep_pins_b: sdmmc2-d47-sleep-1 { |
| 1578 | pins { |
| 1579 | pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ |
| 1580 | <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ |
| 1581 | <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ |
| 1582 | <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ |
| 1583 | }; |
| 1584 | }; |
| 1585 | |
| 1586 | sdmmc2_d47_pins_c: sdmmc2-d47-2 { |
| 1587 | pins { |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 1588 | pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ |
| 1589 | <STM32_PINMUX('A', 15, AF9)>, /* SDMMC2_D5 */ |
| 1590 | <STM32_PINMUX('C', 6, AF10)>, /* SDMMC2_D6 */ |
| 1591 | <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ |
| 1592 | slew-rate = <1>; |
| 1593 | drive-push-pull; |
| 1594 | bias-pull-up; |
| 1595 | }; |
| 1596 | }; |
| 1597 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1598 | sdmmc2_d47_sleep_pins_c: sdmmc2-d47-sleep-2 { |
Patrick Delaunay | 8aee15d | 2020-04-21 12:27:35 +0200 | [diff] [blame] | 1599 | pins { |
| 1600 | pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ |
| 1601 | <STM32_PINMUX('A', 15, ANALOG)>, /* SDMMC2_D5 */ |
| 1602 | <STM32_PINMUX('C', 6, ANALOG)>, /* SDMMC2_D6 */ |
| 1603 | <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ |
| 1604 | }; |
| 1605 | }; |
| 1606 | |
Patrick Delaunay | 6d39705 | 2021-01-11 12:33:36 +0100 | [diff] [blame] | 1607 | sdmmc2_d47_pins_d: sdmmc2-d47-3 { |
| 1608 | pins { |
| 1609 | pinmux = <STM32_PINMUX('A', 8, AF9)>, /* SDMMC2_D4 */ |
| 1610 | <STM32_PINMUX('A', 9, AF10)>, /* SDMMC2_D5 */ |
| 1611 | <STM32_PINMUX('E', 5, AF9)>, /* SDMMC2_D6 */ |
| 1612 | <STM32_PINMUX('C', 7, AF10)>; /* SDMMC2_D7 */ |
| 1613 | }; |
| 1614 | }; |
| 1615 | |
| 1616 | sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { |
| 1617 | pins { |
| 1618 | pinmux = <STM32_PINMUX('A', 8, ANALOG)>, /* SDMMC2_D4 */ |
| 1619 | <STM32_PINMUX('A', 9, ANALOG)>, /* SDMMC2_D5 */ |
| 1620 | <STM32_PINMUX('E', 5, ANALOG)>, /* SDMMC2_D6 */ |
| 1621 | <STM32_PINMUX('C', 7, ANALOG)>; /* SDMMC2_D7 */ |
| 1622 | }; |
| 1623 | }; |
| 1624 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1625 | sdmmc3_b4_pins_a: sdmmc3-b4-0 { |
| 1626 | pins1 { |
| 1627 | pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ |
| 1628 | <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ |
| 1629 | <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ |
| 1630 | <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ |
| 1631 | <STM32_PINMUX('F', 1, AF9)>; /* SDMMC3_CMD */ |
| 1632 | slew-rate = <1>; |
| 1633 | drive-push-pull; |
| 1634 | bias-pull-up; |
| 1635 | }; |
| 1636 | pins2 { |
| 1637 | pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ |
| 1638 | slew-rate = <2>; |
| 1639 | drive-push-pull; |
| 1640 | bias-pull-up; |
| 1641 | }; |
| 1642 | }; |
| 1643 | |
| 1644 | sdmmc3_b4_od_pins_a: sdmmc3-b4-od-0 { |
| 1645 | pins1 { |
| 1646 | pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ |
| 1647 | <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ |
| 1648 | <STM32_PINMUX('F', 5, AF9)>, /* SDMMC3_D2 */ |
| 1649 | <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ |
| 1650 | slew-rate = <1>; |
| 1651 | drive-push-pull; |
| 1652 | bias-pull-up; |
| 1653 | }; |
| 1654 | pins2 { |
| 1655 | pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ |
| 1656 | slew-rate = <2>; |
| 1657 | drive-push-pull; |
| 1658 | bias-pull-up; |
| 1659 | }; |
| 1660 | pins3 { |
| 1661 | pinmux = <STM32_PINMUX('F', 1, AF9)>; /* SDMMC2_CMD */ |
| 1662 | slew-rate = <1>; |
| 1663 | drive-open-drain; |
| 1664 | bias-pull-up; |
| 1665 | }; |
| 1666 | }; |
| 1667 | |
| 1668 | sdmmc3_b4_sleep_pins_a: sdmmc3-b4-sleep-0 { |
| 1669 | pins { |
| 1670 | pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ |
| 1671 | <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ |
| 1672 | <STM32_PINMUX('F', 5, ANALOG)>, /* SDMMC3_D2 */ |
| 1673 | <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ |
| 1674 | <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ |
| 1675 | <STM32_PINMUX('F', 1, ANALOG)>; /* SDMMC3_CMD */ |
| 1676 | }; |
| 1677 | }; |
| 1678 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1679 | sdmmc3_b4_pins_b: sdmmc3-b4-1 { |
| 1680 | pins1 { |
| 1681 | pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ |
| 1682 | <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ |
| 1683 | <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ |
| 1684 | <STM32_PINMUX('D', 7, AF10)>, /* SDMMC3_D3 */ |
| 1685 | <STM32_PINMUX('D', 0, AF10)>; /* SDMMC3_CMD */ |
| 1686 | slew-rate = <1>; |
| 1687 | drive-push-pull; |
| 1688 | bias-pull-up; |
| 1689 | }; |
| 1690 | pins2 { |
| 1691 | pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ |
| 1692 | slew-rate = <2>; |
| 1693 | drive-push-pull; |
| 1694 | bias-pull-up; |
| 1695 | }; |
| 1696 | }; |
| 1697 | |
| 1698 | sdmmc3_b4_od_pins_b: sdmmc3-b4-od-1 { |
| 1699 | pins1 { |
| 1700 | pinmux = <STM32_PINMUX('F', 0, AF9)>, /* SDMMC3_D0 */ |
| 1701 | <STM32_PINMUX('F', 4, AF9)>, /* SDMMC3_D1 */ |
| 1702 | <STM32_PINMUX('D', 5, AF10)>, /* SDMMC3_D2 */ |
| 1703 | <STM32_PINMUX('D', 7, AF10)>; /* SDMMC3_D3 */ |
| 1704 | slew-rate = <1>; |
| 1705 | drive-push-pull; |
| 1706 | bias-pull-up; |
| 1707 | }; |
| 1708 | pins2 { |
| 1709 | pinmux = <STM32_PINMUX('G', 15, AF10)>; /* SDMMC3_CK */ |
| 1710 | slew-rate = <2>; |
| 1711 | drive-push-pull; |
| 1712 | bias-pull-up; |
| 1713 | }; |
| 1714 | pins3 { |
| 1715 | pinmux = <STM32_PINMUX('D', 0, AF10)>; /* SDMMC2_CMD */ |
| 1716 | slew-rate = <1>; |
| 1717 | drive-open-drain; |
| 1718 | bias-pull-up; |
| 1719 | }; |
| 1720 | }; |
| 1721 | |
| 1722 | sdmmc3_b4_sleep_pins_b: sdmmc3-b4-sleep-1 { |
| 1723 | pins { |
| 1724 | pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* SDMMC3_D0 */ |
| 1725 | <STM32_PINMUX('F', 4, ANALOG)>, /* SDMMC3_D1 */ |
| 1726 | <STM32_PINMUX('D', 5, ANALOG)>, /* SDMMC3_D2 */ |
| 1727 | <STM32_PINMUX('D', 7, ANALOG)>, /* SDMMC3_D3 */ |
| 1728 | <STM32_PINMUX('G', 15, ANALOG)>, /* SDMMC3_CK */ |
| 1729 | <STM32_PINMUX('D', 0, ANALOG)>; /* SDMMC3_CMD */ |
| 1730 | }; |
| 1731 | }; |
| 1732 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1733 | spdifrx_pins_a: spdifrx-0 { |
| 1734 | pins { |
| 1735 | pinmux = <STM32_PINMUX('G', 12, AF8)>; /* SPDIF_IN1 */ |
| 1736 | bias-disable; |
| 1737 | }; |
| 1738 | }; |
| 1739 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1740 | spdifrx_sleep_pins_a: spdifrx-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1741 | pins { |
| 1742 | pinmux = <STM32_PINMUX('G', 12, ANALOG)>; /* SPDIF_IN1 */ |
| 1743 | }; |
| 1744 | }; |
| 1745 | |
| 1746 | spi2_pins_a: spi2-0 { |
| 1747 | pins1 { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1748 | pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI1_SCK */ |
| 1749 | <STM32_PINMUX('I', 3, AF5)>; /* SPI1_MOSI */ |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1750 | bias-disable; |
| 1751 | drive-push-pull; |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1752 | slew-rate = <1>; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1753 | }; |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1754 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1755 | pins2 { |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1756 | pinmux = <STM32_PINMUX('I', 2, AF5)>; /* SPI1_MISO */ |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1757 | bias-disable; |
| 1758 | }; |
| 1759 | }; |
| 1760 | |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1761 | spi4_pins_a: spi4-0 { |
| 1762 | pins { |
| 1763 | pinmux = <STM32_PINMUX('E', 12, AF5)>, /* SPI4_SCK */ |
| 1764 | <STM32_PINMUX('E', 6, AF5)>; /* SPI4_MOSI */ |
| 1765 | bias-disable; |
| 1766 | drive-push-pull; |
| 1767 | slew-rate = <1>; |
| 1768 | }; |
| 1769 | pins2 { |
| 1770 | pinmux = <STM32_PINMUX('E', 13, AF5)>; /* SPI4_MISO */ |
| 1771 | bias-disable; |
| 1772 | }; |
| 1773 | }; |
| 1774 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1775 | stusb1600_pins_a: stusb1600-0 { |
Patrick Delaunay | 6d39705 | 2021-01-11 12:33:36 +0100 | [diff] [blame] | 1776 | pins { |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 1777 | pinmux = <STM32_PINMUX('I', 11, GPIO)>; |
Patrick Delaunay | 6d39705 | 2021-01-11 12:33:36 +0100 | [diff] [blame] | 1778 | bias-pull-up; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 1779 | }; |
| 1780 | }; |
| 1781 | |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1782 | uart4_pins_a: uart4-0 { |
| 1783 | pins1 { |
| 1784 | pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ |
| 1785 | bias-disable; |
| 1786 | drive-push-pull; |
| 1787 | slew-rate = <0>; |
| 1788 | }; |
| 1789 | pins2 { |
| 1790 | pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ |
| 1791 | bias-disable; |
| 1792 | }; |
| 1793 | }; |
| 1794 | |
| 1795 | uart4_idle_pins_a: uart4-idle-0 { |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 1796 | pins1 { |
| 1797 | pinmux = <STM32_PINMUX('G', 11, ANALOG)>; /* UART4_TX */ |
| 1798 | }; |
| 1799 | pins2 { |
| 1800 | pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ |
| 1801 | bias-disable; |
| 1802 | }; |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1803 | }; |
| 1804 | |
| 1805 | uart4_sleep_pins_a: uart4-sleep-0 { |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 1806 | pins { |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1807 | pinmux = <STM32_PINMUX('G', 11, ANALOG)>, /* UART4_TX */ |
| 1808 | <STM32_PINMUX('B', 2, ANALOG)>; /* UART4_RX */ |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 1809 | }; |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1810 | }; |
| 1811 | |
| 1812 | uart4_pins_b: uart4-1 { |
| 1813 | pins1 { |
| 1814 | pinmux = <STM32_PINMUX('D', 1, AF8)>; /* UART4_TX */ |
| 1815 | bias-disable; |
| 1816 | drive-push-pull; |
| 1817 | slew-rate = <0>; |
| 1818 | }; |
| 1819 | pins2 { |
| 1820 | pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ |
| 1821 | bias-disable; |
| 1822 | }; |
| 1823 | }; |
| 1824 | |
| 1825 | uart4_pins_c: uart4-2 { |
| 1826 | pins1 { |
| 1827 | pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */ |
| 1828 | bias-disable; |
| 1829 | drive-push-pull; |
| 1830 | slew-rate = <0>; |
| 1831 | }; |
| 1832 | pins2 { |
| 1833 | pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */ |
| 1834 | bias-disable; |
| 1835 | }; |
| 1836 | }; |
| 1837 | |
| 1838 | uart7_pins_a: uart7-0 { |
| 1839 | pins1 { |
| 1840 | pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ |
| 1841 | bias-disable; |
| 1842 | drive-push-pull; |
| 1843 | slew-rate = <0>; |
| 1844 | }; |
| 1845 | pins2 { |
| 1846 | pinmux = <STM32_PINMUX('E', 7, AF7)>, /* UART7_RX */ |
| 1847 | <STM32_PINMUX('E', 10, AF7)>, /* UART7_CTS */ |
| 1848 | <STM32_PINMUX('E', 9, AF7)>; /* UART7_RTS */ |
| 1849 | bias-disable; |
| 1850 | }; |
| 1851 | }; |
| 1852 | |
| 1853 | uart7_pins_b: uart7-1 { |
| 1854 | pins1 { |
| 1855 | pinmux = <STM32_PINMUX('F', 7, AF7)>; /* UART7_TX */ |
| 1856 | bias-disable; |
| 1857 | drive-push-pull; |
| 1858 | slew-rate = <0>; |
| 1859 | }; |
| 1860 | pins2 { |
| 1861 | pinmux = <STM32_PINMUX('F', 6, AF7)>; /* UART7_RX */ |
| 1862 | bias-disable; |
| 1863 | }; |
| 1864 | }; |
| 1865 | |
| 1866 | uart7_pins_c: uart7-2 { |
| 1867 | pins1 { |
| 1868 | pinmux = <STM32_PINMUX('E', 8, AF7)>; /* UART7_TX */ |
| 1869 | bias-disable; |
| 1870 | drive-push-pull; |
| 1871 | slew-rate = <0>; |
| 1872 | }; |
| 1873 | pins2 { |
| 1874 | pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 1875 | bias-pull-up; |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1876 | }; |
| 1877 | }; |
| 1878 | |
| 1879 | uart7_idle_pins_c: uart7-idle-2 { |
| 1880 | pins1 { |
| 1881 | pinmux = <STM32_PINMUX('E', 8, ANALOG)>; /* UART7_TX */ |
| 1882 | }; |
| 1883 | pins2 { |
| 1884 | pinmux = <STM32_PINMUX('E', 7, AF7)>; /* UART7_RX */ |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 1885 | bias-pull-up; |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1886 | }; |
| 1887 | }; |
| 1888 | |
| 1889 | uart7_sleep_pins_c: uart7-sleep-2 { |
| 1890 | pins { |
| 1891 | pinmux = <STM32_PINMUX('E', 8, ANALOG)>, /* UART7_TX */ |
| 1892 | <STM32_PINMUX('E', 7, ANALOG)>; /* UART7_RX */ |
| 1893 | }; |
| 1894 | }; |
| 1895 | |
| 1896 | uart8_pins_a: uart8-0 { |
| 1897 | pins1 { |
| 1898 | pinmux = <STM32_PINMUX('E', 1, AF8)>; /* UART8_TX */ |
| 1899 | bias-disable; |
| 1900 | drive-push-pull; |
| 1901 | slew-rate = <0>; |
| 1902 | }; |
| 1903 | pins2 { |
| 1904 | pinmux = <STM32_PINMUX('E', 0, AF8)>; /* UART8_RX */ |
| 1905 | bias-disable; |
| 1906 | }; |
| 1907 | }; |
| 1908 | |
Patrick Delaunay | 6d39705 | 2021-01-11 12:33:36 +0100 | [diff] [blame] | 1909 | uart8_rtscts_pins_a: uart8rtscts-0 { |
| 1910 | pins { |
| 1911 | pinmux = <STM32_PINMUX('G', 7, AF8)>, /* UART8_RTS */ |
| 1912 | <STM32_PINMUX('G', 10, AF8)>; /* UART8_CTS */ |
| 1913 | bias-disable; |
| 1914 | }; |
| 1915 | }; |
| 1916 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 1917 | usart2_pins_a: usart2-0 { |
| 1918 | pins1 { |
| 1919 | pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ |
| 1920 | <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ |
| 1921 | bias-disable; |
| 1922 | drive-push-pull; |
| 1923 | slew-rate = <0>; |
| 1924 | }; |
| 1925 | pins2 { |
| 1926 | pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ |
| 1927 | <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ |
| 1928 | bias-disable; |
| 1929 | }; |
| 1930 | }; |
| 1931 | |
| 1932 | usart2_sleep_pins_a: usart2-sleep-0 { |
| 1933 | pins { |
| 1934 | pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ |
| 1935 | <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ |
| 1936 | <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ |
| 1937 | <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ |
| 1938 | }; |
| 1939 | }; |
| 1940 | |
| 1941 | usart2_pins_b: usart2-1 { |
| 1942 | pins1 { |
| 1943 | pinmux = <STM32_PINMUX('F', 5, AF7)>, /* USART2_TX */ |
| 1944 | <STM32_PINMUX('A', 1, AF7)>; /* USART2_RTS */ |
| 1945 | bias-disable; |
| 1946 | drive-push-pull; |
| 1947 | slew-rate = <0>; |
| 1948 | }; |
| 1949 | pins2 { |
| 1950 | pinmux = <STM32_PINMUX('F', 4, AF7)>, /* USART2_RX */ |
| 1951 | <STM32_PINMUX('E', 15, AF7)>; /* USART2_CTS_NSS */ |
| 1952 | bias-disable; |
| 1953 | }; |
| 1954 | }; |
| 1955 | |
| 1956 | usart2_sleep_pins_b: usart2-sleep-1 { |
| 1957 | pins { |
| 1958 | pinmux = <STM32_PINMUX('F', 5, ANALOG)>, /* USART2_TX */ |
| 1959 | <STM32_PINMUX('A', 1, ANALOG)>, /* USART2_RTS */ |
| 1960 | <STM32_PINMUX('F', 4, ANALOG)>, /* USART2_RX */ |
| 1961 | <STM32_PINMUX('E', 15, ANALOG)>; /* USART2_CTS_NSS */ |
| 1962 | }; |
| 1963 | }; |
| 1964 | |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1965 | usart2_pins_c: usart2-2 { |
| 1966 | pins1 { |
| 1967 | pinmux = <STM32_PINMUX('D', 5, AF7)>, /* USART2_TX */ |
| 1968 | <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ |
| 1969 | bias-disable; |
| 1970 | drive-push-pull; |
| 1971 | slew-rate = <3>; |
| 1972 | }; |
| 1973 | pins2 { |
| 1974 | pinmux = <STM32_PINMUX('D', 6, AF7)>, /* USART2_RX */ |
| 1975 | <STM32_PINMUX('D', 3, AF7)>; /* USART2_CTS_NSS */ |
| 1976 | bias-disable; |
| 1977 | }; |
| 1978 | }; |
| 1979 | |
| 1980 | usart2_idle_pins_c: usart2-idle-2 { |
| 1981 | pins1 { |
| 1982 | pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1983 | <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ |
| 1984 | }; |
| 1985 | pins2 { |
Patrick Delaunay | e48a0d4 | 2021-06-29 12:01:07 +0200 | [diff] [blame] | 1986 | pinmux = <STM32_PINMUX('D', 4, AF7)>; /* USART2_RTS */ |
| 1987 | bias-disable; |
| 1988 | drive-push-pull; |
| 1989 | slew-rate = <3>; |
| 1990 | }; |
| 1991 | pins3 { |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 1992 | pinmux = <STM32_PINMUX('D', 6, AF7)>; /* USART2_RX */ |
| 1993 | bias-disable; |
| 1994 | }; |
| 1995 | }; |
| 1996 | |
| 1997 | usart2_sleep_pins_c: usart2-sleep-2 { |
| 1998 | pins { |
| 1999 | pinmux = <STM32_PINMUX('D', 5, ANALOG)>, /* USART2_TX */ |
| 2000 | <STM32_PINMUX('D', 4, ANALOG)>, /* USART2_RTS */ |
| 2001 | <STM32_PINMUX('D', 6, ANALOG)>, /* USART2_RX */ |
| 2002 | <STM32_PINMUX('D', 3, ANALOG)>; /* USART2_CTS_NSS */ |
| 2003 | }; |
| 2004 | }; |
| 2005 | |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 2006 | usart3_pins_a: usart3-0 { |
| 2007 | pins1 { |
| 2008 | pinmux = <STM32_PINMUX('B', 10, AF7)>; /* USART3_TX */ |
| 2009 | bias-disable; |
| 2010 | drive-push-pull; |
| 2011 | slew-rate = <0>; |
| 2012 | }; |
| 2013 | pins2 { |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2014 | pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ |
| 2015 | bias-disable; |
| 2016 | }; |
| 2017 | }; |
| 2018 | |
| 2019 | usart3_pins_b: usart3-1 { |
| 2020 | pins1 { |
| 2021 | pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ |
| 2022 | <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ |
| 2023 | bias-disable; |
| 2024 | drive-push-pull; |
| 2025 | slew-rate = <0>; |
| 2026 | }; |
| 2027 | pins2 { |
| 2028 | pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ |
| 2029 | <STM32_PINMUX('I', 10, AF8)>; /* USART3_CTS_NSS */ |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 2030 | bias-pull-up; |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2031 | }; |
| 2032 | }; |
| 2033 | |
| 2034 | usart3_idle_pins_b: usart3-idle-1 { |
| 2035 | pins1 { |
| 2036 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2037 | <STM32_PINMUX('I', 10, ANALOG)>; /* USART3_CTS_NSS */ |
| 2038 | }; |
| 2039 | pins2 { |
Patrick Delaunay | e48a0d4 | 2021-06-29 12:01:07 +0200 | [diff] [blame] | 2040 | pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ |
| 2041 | bias-disable; |
| 2042 | drive-push-pull; |
| 2043 | slew-rate = <0>; |
| 2044 | }; |
| 2045 | pins3 { |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2046 | pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 2047 | bias-pull-up; |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2048 | }; |
| 2049 | }; |
| 2050 | |
| 2051 | usart3_sleep_pins_b: usart3-sleep-1 { |
| 2052 | pins { |
| 2053 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
| 2054 | <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ |
| 2055 | <STM32_PINMUX('I', 10, ANALOG)>, /* USART3_CTS_NSS */ |
| 2056 | <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ |
| 2057 | }; |
| 2058 | }; |
| 2059 | |
| 2060 | usart3_pins_c: usart3-2 { |
| 2061 | pins1 { |
| 2062 | pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ |
| 2063 | <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ |
| 2064 | bias-disable; |
| 2065 | drive-push-pull; |
| 2066 | slew-rate = <0>; |
| 2067 | }; |
| 2068 | pins2 { |
| 2069 | pinmux = <STM32_PINMUX('B', 12, AF8)>, /* USART3_RX */ |
| 2070 | <STM32_PINMUX('B', 13, AF7)>; /* USART3_CTS_NSS */ |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 2071 | bias-pull-up; |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2072 | }; |
| 2073 | }; |
| 2074 | |
| 2075 | usart3_idle_pins_c: usart3-idle-2 { |
| 2076 | pins1 { |
| 2077 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2078 | <STM32_PINMUX('B', 13, ANALOG)>; /* USART3_CTS_NSS */ |
| 2079 | }; |
| 2080 | pins2 { |
Patrick Delaunay | e48a0d4 | 2021-06-29 12:01:07 +0200 | [diff] [blame] | 2081 | pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ |
| 2082 | bias-disable; |
| 2083 | drive-push-pull; |
| 2084 | slew-rate = <0>; |
| 2085 | }; |
| 2086 | pins3 { |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 2087 | pinmux = <STM32_PINMUX('B', 12, AF8)>; /* USART3_RX */ |
Patrick Delaunay | b3f8d83 | 2022-01-31 16:07:54 +0100 | [diff] [blame] | 2088 | bias-pull-up; |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 2089 | }; |
| 2090 | }; |
| 2091 | |
Patrick Delaunay | 551efca | 2020-09-16 10:01:32 +0200 | [diff] [blame] | 2092 | usart3_sleep_pins_c: usart3-sleep-2 { |
| 2093 | pins { |
| 2094 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
| 2095 | <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ |
| 2096 | <STM32_PINMUX('B', 13, ANALOG)>, /* USART3_CTS_NSS */ |
| 2097 | <STM32_PINMUX('B', 12, ANALOG)>; /* USART3_RX */ |
| 2098 | }; |
| 2099 | }; |
| 2100 | |
Patrick Delaunay | 6f18219 | 2022-04-26 15:38:05 +0200 | [diff] [blame] | 2101 | usart3_pins_d: usart3-3 { |
| 2102 | pins1 { |
| 2103 | pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ |
| 2104 | <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ |
| 2105 | bias-disable; |
| 2106 | drive-push-pull; |
| 2107 | slew-rate = <0>; |
| 2108 | }; |
| 2109 | pins2 { |
| 2110 | pinmux = <STM32_PINMUX('D', 9, AF7)>, /* USART3_RX */ |
| 2111 | <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ |
| 2112 | bias-disable; |
| 2113 | }; |
| 2114 | }; |
| 2115 | |
| 2116 | usart3_idle_pins_d: usart3-idle-3 { |
| 2117 | pins1 { |
| 2118 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
| 2119 | <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ |
| 2120 | <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ |
| 2121 | }; |
| 2122 | pins2 { |
| 2123 | pinmux = <STM32_PINMUX('D', 9, AF7)>; /* USART3_RX */ |
| 2124 | bias-disable; |
| 2125 | }; |
| 2126 | }; |
| 2127 | |
| 2128 | usart3_sleep_pins_d: usart3-sleep-3 { |
| 2129 | pins { |
| 2130 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
| 2131 | <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ |
| 2132 | <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ |
| 2133 | <STM32_PINMUX('D', 9, ANALOG)>; /* USART3_RX */ |
| 2134 | }; |
| 2135 | }; |
| 2136 | |
Marek Vasut | adbb830 | 2022-06-13 11:55:16 +0200 | [diff] [blame^] | 2137 | usart3_pins_e: usart3-4 { |
| 2138 | pins1 { |
| 2139 | pinmux = <STM32_PINMUX('B', 10, AF7)>, /* USART3_TX */ |
| 2140 | <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ |
| 2141 | bias-disable; |
| 2142 | drive-push-pull; |
| 2143 | slew-rate = <0>; |
| 2144 | }; |
| 2145 | pins2 { |
| 2146 | pinmux = <STM32_PINMUX('B', 11, AF7)>, /* USART3_RX */ |
| 2147 | <STM32_PINMUX('D', 11, AF7)>; /* USART3_CTS_NSS */ |
| 2148 | bias-pull-up; |
| 2149 | }; |
| 2150 | }; |
| 2151 | |
| 2152 | usart3_idle_pins_e: usart3-idle-4 { |
| 2153 | pins1 { |
| 2154 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
| 2155 | <STM32_PINMUX('D', 11, ANALOG)>; /* USART3_CTS_NSS */ |
| 2156 | }; |
| 2157 | pins2 { |
| 2158 | pinmux = <STM32_PINMUX('G', 8, AF8)>; /* USART3_RTS */ |
| 2159 | bias-disable; |
| 2160 | drive-push-pull; |
| 2161 | slew-rate = <0>; |
| 2162 | }; |
| 2163 | pins3 { |
| 2164 | pinmux = <STM32_PINMUX('B', 11, AF7)>; /* USART3_RX */ |
| 2165 | bias-pull-up; |
| 2166 | }; |
| 2167 | }; |
| 2168 | |
| 2169 | usart3_sleep_pins_e: usart3-sleep-4 { |
| 2170 | pins { |
| 2171 | pinmux = <STM32_PINMUX('B', 10, ANALOG)>, /* USART3_TX */ |
| 2172 | <STM32_PINMUX('G', 8, ANALOG)>, /* USART3_RTS */ |
| 2173 | <STM32_PINMUX('D', 11, ANALOG)>, /* USART3_CTS_NSS */ |
| 2174 | <STM32_PINMUX('B', 11, ANALOG)>; /* USART3_RX */ |
| 2175 | }; |
| 2176 | }; |
| 2177 | |
Patrick Delaunay | df0d20a | 2020-04-30 15:52:46 +0200 | [diff] [blame] | 2178 | usbotg_hs_pins_a: usbotg-hs-0 { |
| 2179 | pins { |
| 2180 | pinmux = <STM32_PINMUX('A', 10, ANALOG)>; /* OTG_ID */ |
| 2181 | }; |
| 2182 | }; |
| 2183 | |
| 2184 | usbotg_fs_dp_dm_pins_a: usbotg-fs-dp-dm-0 { |
| 2185 | pins { |
| 2186 | pinmux = <STM32_PINMUX('A', 11, ANALOG)>, /* OTG_FS_DM */ |
| 2187 | <STM32_PINMUX('A', 12, ANALOG)>; /* OTG_FS_DP */ |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 2188 | }; |
| 2189 | }; |
| 2190 | }; |
| 2191 | |
| 2192 | &pinctrl_z { |
| 2193 | i2c2_pins_b2: i2c2-0 { |
| 2194 | pins { |
| 2195 | pinmux = <STM32_PINMUX('Z', 0, AF3)>; /* I2C2_SCL */ |
| 2196 | bias-disable; |
| 2197 | drive-open-drain; |
| 2198 | slew-rate = <0>; |
| 2199 | }; |
| 2200 | }; |
| 2201 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 2202 | i2c2_sleep_pins_b2: i2c2-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 2203 | pins { |
| 2204 | pinmux = <STM32_PINMUX('Z', 0, ANALOG)>; /* I2C2_SCL */ |
| 2205 | }; |
| 2206 | }; |
| 2207 | |
| 2208 | i2c4_pins_a: i2c4-0 { |
| 2209 | pins { |
| 2210 | pinmux = <STM32_PINMUX('Z', 4, AF6)>, /* I2C4_SCL */ |
| 2211 | <STM32_PINMUX('Z', 5, AF6)>; /* I2C4_SDA */ |
| 2212 | bias-disable; |
| 2213 | drive-open-drain; |
| 2214 | slew-rate = <0>; |
| 2215 | }; |
| 2216 | }; |
| 2217 | |
Patrick Delaunay | cdc2ca1 | 2020-07-06 13:26:53 +0200 | [diff] [blame] | 2218 | i2c4_sleep_pins_a: i2c4-sleep-0 { |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 2219 | pins { |
| 2220 | pinmux = <STM32_PINMUX('Z', 4, ANALOG)>, /* I2C4_SCL */ |
| 2221 | <STM32_PINMUX('Z', 5, ANALOG)>; /* I2C4_SDA */ |
| 2222 | }; |
| 2223 | }; |
| 2224 | |
Patrick Delaunay | e48a0d4 | 2021-06-29 12:01:07 +0200 | [diff] [blame] | 2225 | i2c6_pins_a: i2c6-0 { |
| 2226 | pins { |
| 2227 | pinmux = <STM32_PINMUX('Z', 6, AF2)>, /* I2C6_SCL */ |
| 2228 | <STM32_PINMUX('Z', 7, AF2)>; /* I2C6_SDA */ |
| 2229 | bias-disable; |
| 2230 | drive-open-drain; |
| 2231 | slew-rate = <0>; |
| 2232 | }; |
| 2233 | }; |
| 2234 | |
| 2235 | i2c6_sleep_pins_a: i2c6-sleep-0 { |
| 2236 | pins { |
| 2237 | pinmux = <STM32_PINMUX('Z', 6, ANALOG)>, /* I2C6_SCL */ |
| 2238 | <STM32_PINMUX('Z', 7, ANALOG)>; /* I2C6_SDA */ |
| 2239 | }; |
| 2240 | }; |
| 2241 | |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 2242 | spi1_pins_a: spi1-0 { |
| 2243 | pins1 { |
| 2244 | pinmux = <STM32_PINMUX('Z', 0, AF5)>, /* SPI1_SCK */ |
| 2245 | <STM32_PINMUX('Z', 2, AF5)>; /* SPI1_MOSI */ |
| 2246 | bias-disable; |
| 2247 | drive-push-pull; |
| 2248 | slew-rate = <1>; |
| 2249 | }; |
| 2250 | |
| 2251 | pins2 { |
| 2252 | pinmux = <STM32_PINMUX('Z', 1, AF5)>; /* SPI1_MISO */ |
| 2253 | bias-disable; |
| 2254 | }; |
| 2255 | }; |
Patrick Delaunay | 48c5e90 | 2020-03-06 17:54:41 +0100 | [diff] [blame] | 2256 | }; |