blob: ff7eaf0f20e1a4255f334bef50f4ecb5460b9584 [file] [log] [blame]
developere20fe272022-05-20 11:22:26 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2022 MediaTek Inc. All rights reserved.
4 *
5 * Author: Weijie Gao <weijie.gao@mediatek.com>
6 */
7
8/dts-v1/;
9
10#include "mt7621.dtsi"
11
12/ {
13 compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc";
14 model = "MediaTek MT7621 RFB (SPI-NOR)";
15
16 aliases {
17 serial0 = &uart0;
18 spi0 = &spi;
19 };
20
21 chosen {
22 stdout-path = &uart0;
23 };
24};
25
26&pinctrl {
27 state_default: pin_state {
28 gpios {
29 groups = "i2c", "uart3", "pcie reset";
30 function = "gpio";
31 };
32
33 wdt {
34 groups = "wdt";
35 function = "wdt rst";
36 };
37
38 jtag {
39 groups = "jtag";
40 function = "jtag";
41 };
42 };
43};
44
45&uart0 {
46 status = "okay";
47};
48
49&gpio {
50 status = "okay";
51};
52
53&spi {
54 status = "okay";
55 num-cs = <2>;
56
57 spi-flash@0 {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 compatible = "jedec,spi-nor";
61 spi-max-frequency = <25000000>;
62 reg = <0>;
63 };
64};
65
66&eth {
67 status = "okay";
68};
69
70&mmc {
71 cap-sd-highspeed;
72
73 status = "okay";
74};
75
76&ssusb {
77 status = "okay";
78};
79
80&u3phy {
81 status = "okay";
82};