| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Cross Bar Switch Internal Memory Map |
| 4 | * |
| 5 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. |
| 6 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) |
| TsiChungLiew | 25ebc30 | 2008-01-14 15:30:15 -0600 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CROSSBAR_H__ |
| 10 | #define __CROSSBAR_H__ |
| 11 | |
| 12 | /********************************************************************* |
| 13 | * Cross-bar switch (XBS) |
| 14 | *********************************************************************/ |
| 15 | typedef struct xbs { |
| 16 | u32 prs1; /* 0x100 Priority Register Slave 1 */ |
| 17 | u32 res1[3]; /* 0x104 - 0F */ |
| 18 | u32 crs1; /* 0x110 Control Register Slave 1 */ |
| 19 | u32 res2[187]; /* 0x114 - 0x3FF */ |
| 20 | |
| 21 | u32 prs4; /* 0x400 Priority Register Slave 4 */ |
| 22 | u32 res3[3]; /* 0x404 - 0F */ |
| 23 | u32 crs4; /* 0x410 Control Register Slave 4 */ |
| 24 | u32 res4[123]; /* 0x414 - 0x5FF */ |
| 25 | |
| 26 | u32 prs6; /* 0x600 Priority Register Slave 6 */ |
| 27 | u32 res5[3]; /* 0x604 - 0F */ |
| 28 | u32 crs6; /* 0x610 Control Register Slave 6 */ |
| 29 | u32 res6[59]; /* 0x614 - 0x6FF */ |
| 30 | |
| 31 | u32 prs7; /* 0x700 Priority Register Slave 7 */ |
| 32 | u32 res7[3]; /* 0x704 - 0F */ |
| 33 | u32 crs7; /* 0x710 Control Register Slave 7 */ |
| 34 | } xbs_t; |
| 35 | |
| 36 | /* Bit definitions and macros for PRS group */ |
| 37 | #define XBS_PRS_M0(x) (((x)&0x00000007)) /* Core */ |
| 38 | #define XBS_PRS_M1(x) (((x)&0x00000007)<<4) /* eDMA */ |
| 39 | #define XBS_PRS_M2(x) (((x)&0x00000007)<<8) /* FEC0 */ |
| 40 | #define XBS_PRS_M3(x) (((x)&0x00000007)<<12) /* FEC1 */ |
| 41 | #define XBS_PRS_M5(x) (((x)&0x00000007)<<20) /* PCI controller */ |
| 42 | #define XBS_PRS_M6(x) (((x)&0x00000007)<<24) /* USB OTG */ |
| 43 | #define XBS_PRS_M7(x) (((x)&0x00000007)<<28) /* Serial Boot */ |
| 44 | |
| 45 | /* Bit definitions and macros for CRS group */ |
| 46 | #define XBS_CRS_PARK(x) (((x)&0x00000007)) /* Master parking ctrl */ |
| 47 | #define XBS_CRS_PCTL(x) (((x)&0x00000003)<<4) /* Parking mode ctrl */ |
| 48 | #define XBS_CRS_ARB (0x00000100) /* Arbitration Mode */ |
| 49 | #define XBS_CRS_RO (0x80000000) /* Read Only */ |
| 50 | |
| 51 | #define XBS_CRS_PCTL_PARK_FIELD (0) |
| 52 | #define XBS_CRS_PCTL_PARK_ON_LAST (1) |
| 53 | #define XBS_CRS_PCTL_PARK_NONE (2) |
| 54 | #define XBS_CRS_PCTL_PARK_CORE (0) |
| 55 | #define XBS_CRS_PCTL_PARK_EDMA (1) |
| 56 | #define XBS_CRS_PCTL_PARK_FEC0 (2) |
| 57 | #define XBS_CRS_PCTL_PARK_FEC1 (3) |
| 58 | #define XBS_CRS_PCTL_PARK_PCI (5) |
| 59 | #define XBS_CRS_PCTL_PARK_USB (6) |
| 60 | #define XBS_CRS_PCTL_PARK_SBF (7) |
| 61 | |
| 62 | #endif /* __CROSSBAR_H__ */ |