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Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00001/*
2 * Copyright (C) 2011 by Vladimir Zapolskiy <vz@mleia.com>
3 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +00005 */
6
7#include <common.h>
8#include <asm/arch/cpu.h>
9#include <asm/arch/clk.h>
10#include <asm/arch/uart.h>
Albert ARIBAUD \(3ADEV\)24bfa9d2015-03-31 11:40:47 +020011#include <asm/arch/mux.h>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +000012#include <asm/io.h>
Albert ARIBAUD \(3ADEV\)eb135ad2015-03-31 11:40:46 +020013#include <dm.h>
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +000014
15static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
16static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE;
Albert ARIBAUD \(3ADEV\)24bfa9d2015-03-31 11:40:47 +020017static struct mux_regs *mux = (struct mux_regs *)MUX_BASE;
Vladimir Zapolskiy6b20ef82012-04-19 04:33:08 +000018
19void lpc32xx_uart_init(unsigned int uart_id)
20{
21 if (uart_id < 1 || uart_id > 7)
22 return;
23
24 /* Disable loopback mode, if it is set by S1L bootloader */
25 clrbits_le32(&ctrl->loop,
26 UART_LOOPBACK(CONFIG_SYS_LPC32XX_UART));
27
28 if (uart_id < 3 || uart_id > 6)
29 return;
30
31 /* Enable UART system clock */
32 setbits_le32(&clk->uartclk_ctrl, CLK_UART(uart_id));
33
34 /* Set UART into autoclock mode */
35 clrsetbits_le32(&ctrl->clkmode,
36 UART_CLKMODE_MASK(uart_id),
37 UART_CLKMODE_AUTO(uart_id));
38
39 /* Bypass pre-divider of UART clock */
40 writel(CLK_UART_X_DIV(1) | CLK_UART_Y_DIV(1),
41 &clk->u3clk + (uart_id - 3));
42}
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +020043
Sylvain Lemieux90a837f2015-08-10 08:16:31 -040044void lpc32xx_dma_init(void)
45{
46 /* Enable DMA interface */
Vladimir Zapolskiyb7f8ed22015-08-27 03:16:48 +030047 writel(CLK_DMA_ENABLE, &clk->dmaclk_ctrl);
Sylvain Lemieux90a837f2015-08-10 08:16:31 -040048}
49
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +020050void lpc32xx_mac_init(void)
51{
52 /* Enable MAC interface */
53 writel(CLK_MAC_REG | CLK_MAC_SLAVE | CLK_MAC_MASTER
Vladimir Zapolskiy8bffd712015-07-06 07:22:11 +030054#if defined(CONFIG_RMII)
55 | CLK_MAC_RMII,
56#else
57 | CLK_MAC_MII,
58#endif
59 &clk->macclk_ctrl);
Albert ARIBAUD \(3ADEV\)391e1632015-03-31 11:40:43 +020060}
Albert ARIBAUD \(3ADEV\)7c97f702015-03-31 11:40:44 +020061
62void lpc32xx_mlc_nand_init(void)
63{
64 /* Enable NAND interface */
65 writel(CLK_NAND_MLC | CLK_NAND_MLC_INT, &clk->flashclk_ctrl);
66}
Albert ARIBAUD \(3ADEV\)b23324c2015-03-31 11:40:45 +020067
Vladimir Zapolskiy78f04f02015-07-18 03:07:52 +030068void lpc32xx_slc_nand_init(void)
69{
70 /* Enable SLC NAND interface */
71 writel(CLK_NAND_SLC | CLK_NAND_SLC_SELECT, &clk->flashclk_ctrl);
72}
73
Sylvain Lemieux890cc772015-08-13 15:40:22 -040074void lpc32xx_usb_init(void)
75{
76 /* Do not route the UART 5 Tx/Rx pins to the USB D+ and USB D- pins. */
77 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
78}
79
Albert ARIBAUD \(3ADEV\)b23324c2015-03-31 11:40:45 +020080void lpc32xx_i2c_init(unsigned int devnum)
81{
82 /* Enable I2C interface */
83 uint32_t ctrl = readl(&clk->i2cclk_ctrl);
84 if (devnum == 1)
85 ctrl |= CLK_I2C1_ENABLE;
86 if (devnum == 2)
87 ctrl |= CLK_I2C2_ENABLE;
88 writel(ctrl, &clk->i2cclk_ctrl);
89}
Albert ARIBAUD \(3ADEV\)eb135ad2015-03-31 11:40:46 +020090
91U_BOOT_DEVICE(lpc32xx_gpios) = {
92 .name = "gpio_lpc32xx"
93};
Albert ARIBAUD \(3ADEV\)24bfa9d2015-03-31 11:40:47 +020094
95/* Mux for SCK0, MISO0, MOSI0. We do not use SSEL0. */
96
97#define P_MUX_SET_SSP0 0x1600
98
99void lpc32xx_ssp_init(void)
100{
101 /* Enable SSP0 interface */
102 writel(CLK_SSP0_ENABLE_CLOCK, &clk->ssp_ctrl);
103 /* Mux SSP0 pins */
104 writel(P_MUX_SET_SSP0, &mux->p_mux_set);
105}