blob: 5449a8926c5d2491824a300ed31e27e8596c4352 [file] [log] [blame]
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +02001/*
2 * Copyright (C) Marvell International Ltd. and its affiliates
3 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +02006 */
7
8#include <common.h>
Lei Wen298ae912011-10-18 20:11:42 +05309#include <asm/io.h>
Stefan Roesec2437842014-10-22 12:13:06 +020010#include <asm/arch/soc.h>
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020011
Stefan Roesecd931e12014-10-22 12:13:08 +020012#define UBOOT_CNTR 0 /* counter to use for U-Boot timer */
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020013
14/*
15 * ARM Timers Registers Map
16 */
Stefan Roesecd931e12014-10-22 12:13:08 +020017#define CNTMR_CTRL_REG &tmr_regs->ctrl
18#define CNTMR_RELOAD_REG(tmrnum) &tmr_regs->tmr[tmrnum].reload
19#define CNTMR_VAL_REG(tmrnum) &tmr_regs->tmr[tmrnum].val
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020020
21/*
22 * ARM Timers Control Register
23 * CPU_TIMERS_CTRL_REG (CTCR)
24 */
25#define CTCR_ARM_TIMER_EN_OFFS(cntr) (cntr * 2)
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020026#define CTCR_ARM_TIMER_EN(cntr) (1 << CTCR_ARM_TIMER_EN_OFFS(cntr))
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020027
28#define CTCR_ARM_TIMER_AUTO_OFFS(cntr) ((cntr * 2) + 1)
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020029#define CTCR_ARM_TIMER_AUTO_EN(cntr) (1 << CTCR_ARM_TIMER_AUTO_OFFS(cntr))
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020030
Stefan Roesecd931e12014-10-22 12:13:08 +020031/* Only Armada XP have the 25MHz enable bit (Kirkwood doesn't) */
32#if defined(CONFIG_ARMADA_XP)
33#define CTCR_ARM_TIMER_25MHZ_OFFS(cntr) (cntr + 11)
34#define CTCR_ARM_TIMER_25MHZ(cntr) (1 << CTCR_ARM_TIMER_25MHZ_OFFS(cntr))
35#else
36#define CTCR_ARM_TIMER_25MHZ(cntr) 0
37#endif
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020038
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020039#define TIMER_LOAD_VAL 0xffffffff
40
Stefan Roesecd931e12014-10-22 12:13:08 +020041#define timestamp gd->arch.tbl
42#define lastdec gd->arch.lastinc
43
Stefan Roesea0ecc542015-09-03 12:47:07 +020044static int init_done __attribute__((section(".data"))) = 0;
Stefan Roesed04fe8b2015-07-15 15:36:52 +020045
Stefan Roesecd931e12014-10-22 12:13:08 +020046/* Timer reload and current value registers */
47struct kwtmr_val {
48 u32 reload; /* Timer reload reg */
49 u32 val; /* Timer value reg */
50};
51
52/* Timer registers */
53struct kwtmr_registers {
54 u32 ctrl; /* Timer control reg */
55 u32 pad[3];
56 struct kwtmr_val tmr[4];
57 u32 wdt_reload;
58 u32 wdt_val;
59};
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020060
Heiko Schocher5504dab2011-01-20 22:56:39 +000061DECLARE_GLOBAL_DATA_PTR;
62
Stefan Roesecd931e12014-10-22 12:13:08 +020063static struct kwtmr_registers *tmr_regs =
64 (struct kwtmr_registers *)MVEBU_TIMER_BASE;
65
66static inline ulong read_timer(void)
67{
68 return readl(CNTMR_VAL_REG(UBOOT_CNTR)) / (CONFIG_SYS_TCLK / 1000);
69}
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020070
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020071ulong get_timer_masked(void)
72{
Stefan Roesecd931e12014-10-22 12:13:08 +020073 ulong now = read_timer();
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020074
75 if (lastdec >= now) {
76 /* normal mode */
77 timestamp += lastdec - now;
78 } else {
79 /* we have an overflow ... */
80 timestamp += lastdec +
81 (TIMER_LOAD_VAL / (CONFIG_SYS_TCLK / 1000)) - now;
82 }
83 lastdec = now;
84
85 return timestamp;
86}
87
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020088ulong get_timer(ulong base)
89{
90 return get_timer_masked() - base;
91}
92
Ingo van Lilf0f778a2009-11-24 14:09:21 +010093void __udelay(unsigned long usec)
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +020094{
95 uint current;
96 ulong delayticks;
97
98 current = readl(CNTMR_VAL_REG(UBOOT_CNTR));
99 delayticks = (usec * (CONFIG_SYS_TCLK / 1000000));
100
101 if (current < delayticks) {
102 delayticks -= current;
103 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) < current) ;
104 while ((TIMER_LOAD_VAL - delayticks) <
105 readl(CNTMR_VAL_REG(UBOOT_CNTR))) ;
106 } else {
107 while (readl(CNTMR_VAL_REG(UBOOT_CNTR)) >
108 (current - delayticks)) ;
109 }
110}
111
112/*
113 * init the counter
114 */
115int timer_init(void)
116{
Stefan Roesed04fe8b2015-07-15 15:36:52 +0200117 /* Only init the timer once */
118 if (init_done)
119 return 0;
120 init_done = 1;
121
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +0200122 /* load value into timer */
123 writel(TIMER_LOAD_VAL, CNTMR_RELOAD_REG(UBOOT_CNTR));
124 writel(TIMER_LOAD_VAL, CNTMR_VAL_REG(UBOOT_CNTR));
125
126 /* enable timer in auto reload mode */
Stefan Roesecd931e12014-10-22 12:13:08 +0200127 clrsetbits_le32(CNTMR_CTRL_REG, CTCR_ARM_TIMER_25MHZ(UBOOT_CNTR),
128 CTCR_ARM_TIMER_EN(UBOOT_CNTR) |
129 CTCR_ARM_TIMER_AUTO_EN(UBOOT_CNTR));
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +0200130
131 /* init the timestamp and lastdec value */
Stefan Roesecd931e12014-10-22 12:13:08 +0200132 lastdec = read_timer();
Graeme Russ944a7fe2011-07-15 02:21:14 +0000133 timestamp = 0;
Prafulla Wadaskara09bbe52009-06-20 11:01:53 +0200134
135 return 0;
136}
Prafulla Wadaskarf4ce6ad2012-02-08 14:15:53 +0530137
138/*
139 * This function is derived from PowerPC code (read timebase as long long).
140 * On ARM it just returns the timer value.
141 */
142unsigned long long get_ticks(void)
143{
144 return get_timer(0);
145}
146
147/*
148 * This function is derived from PowerPC code (timebase clock frequency).
149 * On ARM it returns the number of timer ticks per second.
150 */
151ulong get_tbclk (void)
152{
153 return (ulong)CONFIG_SYS_HZ;
154}