blob: 684e9272b7798794096e2fe3812114e05a756218 [file] [log] [blame]
stroese8bc10b32004-12-16 17:33:38 +00001/*
2 * (C) Copyright 2003 Stefan Roese, stefan.roese@esd-electronics.com
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef _universe_h
24#define _universe_h
25
26
27typedef struct _UNIVERSE UNIVERSE;
28typedef struct _SLAVE_IMAGE SLAVE_IMAGE;
29typedef struct _TDMA_CMD_PACKET TDMA_CMD_PACKET;
30
31
32struct _SLAVE_IMAGE {
33 unsigned int ctl; /* Control */
34 unsigned int bs; /* Base */
35 unsigned int bd; /* Bound */
36 unsigned int to; /* Translation */
37 unsigned int reserved;
38};
39
40struct _UNIVERSE {
41 unsigned int pci_id;
42 unsigned int pci_csr;
43 unsigned int pci_class;
44 unsigned int pci_misc0;
45 unsigned int pci_bs;
46 unsigned int spare0[10];
47 unsigned int pci_misc1;
48 unsigned int spare1[48];
49 SLAVE_IMAGE lsi[4];
50 unsigned int spare2[8];
51 unsigned int scyc_ctl;
52 unsigned int scyc_addr;
53 unsigned int scyc_en;
54 unsigned int scyc_cmp;
55 unsigned int scyc_swp;
56 unsigned int lmisc;
57 unsigned int slsi;
58 unsigned int l_cmderr;
59 unsigned int laerr;
60 unsigned int spare3[27];
61 unsigned int dctl;
62 unsigned int dtbc;
63 unsigned int dla;
64 unsigned int spare4[1];
65 unsigned int dva;
66 unsigned int spare5[1];
67 unsigned int dcpp;
68 unsigned int spare6[1];
69 unsigned int dgcs;
70 unsigned int d_llue;
71 unsigned int spare7[54];
72 unsigned int lint_en;
73 unsigned int lint_stat;
74 unsigned int lint_map0;
75 unsigned int lint_map1;
76 unsigned int vint_en;
77 unsigned int vint_stat;
78 unsigned int vint_map0;
79 unsigned int vint_map1;
80 unsigned int statid;
81 unsigned int vx_statid[7];
82 unsigned int spare8[48];
83 unsigned int mast_ctl;
84 unsigned int misc_ctl;
85 unsigned int misc_stat;
86 unsigned int user_am;
87 unsigned int spare9[700];
88 SLAVE_IMAGE vsi[4];
89 unsigned int spare10[8];
90 unsigned int vrai_ctl;
91 unsigned int vrai_bs;
92 unsigned int spare11[2];
93 unsigned int vcsr_ctl;
94 unsigned int vcsr_to;
95 unsigned int v_amerr;
96 unsigned int vaerr;
97 unsigned int spare12[25];
98 unsigned int vcsr_clr;
99 unsigned int vcsr_set;
100 unsigned int vcsr_bs;
101};
102
103#define IRQ_VOWN 0x0001
104#define IRQ_VIRQ1 0x0002
105#define IRQ_VIRQ2 0x0004
106#define IRQ_VIRQ3 0x0008
107#define IRQ_VIRQ4 0x0010
108#define IRQ_VIRQ5 0x0020
109#define IRQ_VIRQ6 0x0040
110#define IRQ_VIRQ7 0x0080
111#define IRQ_DMA 0x0100
112#define IRQ_LERR 0x0200
113#define IRQ_VERR 0x0400
114#define IRQ_res 0x0800
115#define IRQ_IACK 0x1000
116#define IRQ_SWINT 0x2000
117#define IRQ_SYSFAIL 0x4000
118#define IRQ_ACFAIL 0x8000
119
120struct _TDMA_CMD_PACKET {
121 unsigned int dctl; /* DMA Control */
122 unsigned int dtbc; /* Transfer Byte Count */
123 unsigned int dlv; /* PCI Address */
124 unsigned int res1; /* Reserved */
125 unsigned int dva; /* Vme Address */
126 unsigned int res2; /* Reserved */
127 unsigned int dcpp; /* Pointer to Numed Cmd Packet with rPN */
128 unsigned int res3; /* Reserved */
129};
130
131#define VME_AM_A16 0x01
132#define VME_AM_A24 0x02
133#define VME_AM_A32 0x03
134#define VME_AM_Axx 0x03
135#define VME_AM_SUP 0x04
136#define VME_AM_DATA 0x10
137#define VME_AM_PROG 0x20
138#define VME_AM_Mxx 0x30
139
140#define VME_FLAG_D8 0x01
141#define VME_FLAG_D16 0x02
142#define VME_FLAG_D32 0x03
143#define VME_FLAG_Dxx 0x03
144
145#define PCI_MS_MEM 0x01
146#define PCI_MS_IO 0x02
147#define PCI_MS_CONFIG 0x03
148#define PCI_MS_Mxx 0x03
149
150#endif
151
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