blob: 83ea624c51c4768f8e853243a1595b1842aa145f [file] [log] [blame]
Michal Simeka335bd22016-04-07 16:00:11 +02001/*
2 * Configuration for Xilinx ZynqMP zc1751 XM016 DC2
3 *
4 * (C) Copyright 2015 Xilinx, Inc.
5 * Michal Simek <michal.simek@xilinx.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
11#define __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H
12
Michal Simeka335bd22016-04-07 16:00:11 +020013#define CONFIG_ZYNQMP_XHCI_LIST {ZYNQMP_USB1_XHCI_BASEADDR}
14
15#define CONFIG_IDENT_STRING " Xilinx ZynqMP ZC1751 xm016 dc2"
16
17#define CONFIG_KERNEL_FDT_OFST_SIZE \
18 "kernel_offset=0x400000\0" \
19 "fdt_offset=0x2400000\0" \
20 "kernel_size=0x2000000\0" \
21 "fdt_size=0x80000\0" \
22 "board=zc1751-dc2\0"
23
24#include <configs/xilinx_zynqmp.h>
25
26#endif /* __CONFIG_ZYNQMP_ZC1751_XM016_DC2_H */