Mateusz Kulikowski | c7e4fbb | 2016-03-31 23:12:28 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Sample SPMI bus driver |
| 3 | * |
| 4 | * It emulates bus with single pm8916-like pmic that has only GPIO reigsters. |
| 5 | * |
| 6 | * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com> |
| 7 | * |
| 8 | * SPDX-License-Identifier: GPL-2.0+ |
| 9 | */ |
| 10 | |
| 11 | #include <common.h> |
| 12 | #include <dm.h> |
| 13 | #include <errno.h> |
| 14 | #include <spmi/spmi.h> |
| 15 | #include <asm/gpio.h> |
| 16 | #include <asm/io.h> |
| 17 | |
| 18 | DECLARE_GLOBAL_DATA_PTR; |
| 19 | |
| 20 | #define EMUL_GPIO_PID_START 0xC0 |
| 21 | #define EMUL_GPIO_PID_END 0xC3 |
| 22 | |
| 23 | #define EMUL_GPIO_COUNT 4 |
| 24 | |
| 25 | #define EMUL_GPIO_REG_END 0x46 /* Last valid register */ |
| 26 | |
| 27 | #define EMUL_PERM_R 0x1 |
| 28 | #define EMUL_PERM_W 0x2 |
| 29 | #define EMUL_PERM_RW (EMUL_PERM_R | EMUL_PERM_W) |
| 30 | |
| 31 | struct sandbox_emul_fake_regs { |
| 32 | u8 value; |
| 33 | u8 access_mask; |
| 34 | u8 perms; /* Access permissions */ |
| 35 | }; |
| 36 | |
| 37 | struct sandbox_emul_gpio { |
| 38 | struct sandbox_emul_fake_regs r[EMUL_GPIO_REG_END]; /* Fake registers */ |
| 39 | }; |
| 40 | |
| 41 | struct sandbox_spmi_priv { |
| 42 | struct sandbox_emul_gpio gpios[EMUL_GPIO_COUNT]; |
| 43 | }; |
| 44 | |
| 45 | /* Check if valid register was requested */ |
| 46 | static bool check_address_valid(int usid, int pid, int off) |
| 47 | { |
| 48 | if (usid != 0) |
| 49 | return false; |
| 50 | if (pid < EMUL_GPIO_PID_START || pid > EMUL_GPIO_PID_END) |
| 51 | return false; |
| 52 | if (off > EMUL_GPIO_REG_END) |
| 53 | return false; |
| 54 | return true; |
| 55 | } |
| 56 | |
| 57 | static int sandbox_spmi_write(struct udevice *dev, int usid, int pid, int off, |
| 58 | uint8_t val) |
| 59 | { |
| 60 | struct sandbox_spmi_priv *priv = dev_get_priv(dev); |
| 61 | struct sandbox_emul_fake_regs *regs; |
| 62 | |
| 63 | if (!check_address_valid(usid, pid, off)) |
| 64 | return -EIO; |
| 65 | |
| 66 | regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */ |
| 67 | |
| 68 | switch (off) { |
| 69 | case 0x40: /* Control */ |
| 70 | val &= regs[off].access_mask; |
| 71 | if (((val & 0x30) == 0x10) || ((val & 0x30) == 0x20)) { |
| 72 | /* out/inout - set status register */ |
| 73 | regs[0x8].value &= ~0x1; |
| 74 | regs[0x8].value |= val & 0x1; |
| 75 | } |
| 76 | break; |
| 77 | default: |
| 78 | if (regs[off].perms & EMUL_PERM_W) |
| 79 | regs[off].value = val & regs[off].access_mask; |
| 80 | } |
| 81 | return 0; |
| 82 | } |
| 83 | |
| 84 | static int sandbox_spmi_read(struct udevice *dev, int usid, int pid, int off) |
| 85 | { |
| 86 | struct sandbox_spmi_priv *priv = dev_get_priv(dev); |
| 87 | struct sandbox_emul_fake_regs *regs; |
| 88 | |
| 89 | if (!check_address_valid(usid, pid, off)) |
| 90 | return -EIO; |
| 91 | |
| 92 | regs = priv->gpios[pid & 0x3].r; /* Last 3 bits of pid are gpio # */ |
| 93 | |
| 94 | if (regs[0x46].value == 0) /* Block disabled */ |
| 95 | return 0; |
| 96 | |
| 97 | switch (off) { |
| 98 | case 0x8: /* Status */ |
| 99 | if (regs[0x46].value == 0) /* Block disabled */ |
| 100 | return 0; |
| 101 | return regs[off].value; |
| 102 | default: |
| 103 | if (regs[off].perms & EMUL_PERM_R) |
| 104 | return regs[off].value; |
| 105 | else |
| 106 | return 0; |
| 107 | } |
| 108 | } |
| 109 | |
| 110 | static struct dm_spmi_ops sandbox_spmi_ops = { |
| 111 | .read = sandbox_spmi_read, |
| 112 | .write = sandbox_spmi_write, |
| 113 | }; |
| 114 | |
| 115 | static int sandbox_spmi_probe(struct udevice *dev) |
| 116 | { |
| 117 | struct sandbox_spmi_priv *priv = dev_get_priv(dev); |
| 118 | int i; |
| 119 | |
| 120 | for (i = 0; i < EMUL_GPIO_COUNT; ++i) { |
| 121 | struct sandbox_emul_fake_regs *regs = priv->gpios[i].r; |
| 122 | regs[4].perms = EMUL_PERM_R; |
| 123 | regs[4].value = 0x10; |
| 124 | regs[5].perms = EMUL_PERM_R; |
| 125 | regs[5].value = 0x5; |
| 126 | regs[8].access_mask = 0x81; |
| 127 | regs[8].perms = EMUL_PERM_RW; |
| 128 | regs[0x40].access_mask = 0x7F; |
| 129 | regs[0x40].perms = EMUL_PERM_RW; |
| 130 | regs[0x41].access_mask = 7; |
| 131 | regs[0x41].perms = EMUL_PERM_RW; |
| 132 | regs[0x42].access_mask = 7; |
| 133 | regs[0x42].perms = EMUL_PERM_RW; |
| 134 | regs[0x42].value = 0x4; |
| 135 | regs[0x45].access_mask = 0x3F; |
| 136 | regs[0x45].perms = EMUL_PERM_RW; |
| 137 | regs[0x45].value = 0x1; |
| 138 | regs[0x46].access_mask = 0x80; |
| 139 | regs[0x46].perms = EMUL_PERM_RW; |
| 140 | regs[0x46].value = 0x80; |
| 141 | } |
| 142 | return 0; |
| 143 | } |
| 144 | |
| 145 | static const struct udevice_id sandbox_spmi_ids[] = { |
| 146 | { .compatible = "sandbox,spmi" }, |
| 147 | { } |
| 148 | }; |
| 149 | |
| 150 | U_BOOT_DRIVER(msm_spmi) = { |
| 151 | .name = "sandbox_spmi", |
| 152 | .id = UCLASS_SPMI, |
| 153 | .of_match = sandbox_spmi_ids, |
| 154 | .ops = &sandbox_spmi_ops, |
| 155 | .probe = sandbox_spmi_probe, |
| 156 | .priv_auto_alloc_size = sizeof(struct sandbox_spmi_priv), |
| 157 | }; |