arch/arm/dts/r8a77980-v3hsk.dts

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the V3H Starter Kit board
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 * Copyright (C) 2018 Cogent Embedded, Inc.
 */

/dts-v1/;
#include "r8a77980.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Renesas V3H Starter Kit board";
	compatible = "renesas,v3hsk", "renesas,r8a77980";

	aliases {
		i2c0 = &i2c0;
		i2c1 = &i2c1;
		i2c2 = &i2c2;
		i2c3 = &i2c3;
		i2c4 = &i2c4;
		i2c5 = &i2c5;
		serial0 = &scif0;
		ethernet0 = &gether;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	hdmi-out {
		compatible = "hdmi-connector";
		type = "a";

		port {
			hdmi_con: endpoint {
				remote-endpoint = <&adv7511_out>;
			};
		};
	};

	lvds-decoder {
		compatible = "thine,thc63lvd1024";
		vcc-supply = <&vcc3v3_d5>;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				thc63lvd1024_in: endpoint {
					remote-endpoint = <&lvds0_out>;
				};
			};

			port@2 {
				reg = <2>;
				thc63lvd1024_out: endpoint {
					remote-endpoint = <&adv7511_in>;
				};
			};
		};
	};

	memory@48000000 {
		device_type = "memory";
		/* first 128MB is reserved for secure area. */
		reg = <0 0x48000000 0 0x78000000>;
	};

	osc1_clk: osc1-clock {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <148500000>;
	};

	vcc1v8_d4: regulator-0 {
		compatible = "regulator-fixed";
		regulator-name = "VCC1V8_D4";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		regulator-boot-on;
		regulator-always-on;
	};

	vcc3v3_d5: regulator-1 {
		compatible = "regulator-fixed";
		regulator-name = "VCC3V3_D5";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		regulator-always-on;
	};
};

&du {
	clocks = <&cpg CPG_MOD 724>,
		 <&osc1_clk>;
	clock-names = "du.0", "dclkin.0";
	status = "okay";
};

&extal_clk {
	clock-frequency = <16666666>;
};

&extalr_clk {
	clock-frequency = <32768>;
};

&gether {
	pinctrl-0 = <&gether_pins>;
	pinctrl-names = "default";

	phy-mode = "rgmii";
	phy-handle = <&phy0>;
	renesas,no-ether-link;
	status = "okay";

	phy0: ethernet-phy@0 {
		compatible = "ethernet-phy-id0022.1622",
			     "ethernet-phy-ieee802.3-c22";
		reg = <0>;
		interrupt-parent = <&gpio4>;
		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
		reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	};
};

&i2c0 {
	pinctrl-0 = <&i2c0_pins>;
	pinctrl-names = "default";

	status = "okay";
	clock-frequency = <400000>;

	hdmi@39 {
		compatible = "adi,adv7511w";
		#sound-dai-cells = <0>;
		reg = <0x39>;
		interrupt-parent = <&gpio1>;
		interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
		avdd-supply = <&vcc1v8_d4>;
		dvdd-supply = <&vcc1v8_d4>;
		pvdd-supply = <&vcc1v8_d4>;
		bgvdd-supply = <&vcc1v8_d4>;
		dvdd-3v-supply = <&vcc3v3_d5>;

		adi,input-depth = <8>;
		adi,input-colorspace = "rgb";
		adi,input-clock = "1x";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				adv7511_in: endpoint {
					remote-endpoint = <&thc63lvd1024_out>;
				};
			};

			port@1 {
				reg = <1>;
				adv7511_out: endpoint {
					remote-endpoint = <&hdmi_con>;
				};
			};
		};
	};
};

&lvds0 {
	status = "okay";

	ports {
		port@1 {
			lvds0_out: endpoint {
				remote-endpoint = <&thc63lvd1024_in>;
			};
		};
	};
};

&pfc {
	gether_pins: gether {
		groups = "gether_mdio_a", "gether_rgmii",
			 "gether_txcrefclk", "gether_txcrefclk_mega";
		function = "gether";
	};

	i2c0_pins: i2c0 {
		groups = "i2c0";
		function = "i2c0";
	};

	qspi0_pins: qspi0 {
		groups = "qspi0_ctrl", "qspi0_data4";
		function = "qspi0";
	};

	scif0_pins: scif0 {
		groups = "scif0_data";
		function = "scif0";
	};

	scif_clk_pins: scif_clk {
		groups = "scif_clk_b";
		function = "scif_clk";
	};
};

&rpc {
	pinctrl-0 = <&qspi0_pins>;
	pinctrl-names = "default";

	status = "okay";

	flash@0 {
		compatible = "spansion,s25fs512s", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			bootparam@0 {
				reg = <0x00000000 0x040000>;
				read-only;
			};
			cr7@40000 {
				reg = <0x00040000 0x080000>;
				read-only;
			};
			cert_header_sa3@c0000 {
				reg = <0x000c0000 0x080000>;
				read-only;
			};
			bl2@140000 {
				reg = <0x00140000 0x040000>;
				read-only;
			};
			cert_header_sa6@180000 {
				reg = <0x00180000 0x040000>;
				read-only;
			};
			bl31@1c0000 {
				reg = <0x001c0000 0x460000>;
				read-only;
			};
			uboot@640000 {
				reg = <0x00640000 0x0c0000>;
				read-only;
			};
			uboot-env@700000 {
				reg = <0x00700000 0x040000>;
				read-only;
			};
			dtb@740000 {
				reg = <0x00740000 0x080000>;
			};
			kernel@7c0000 {
				reg = <0x007c0000 0x1400000>;
			};
			user@1bc0000 {
				reg = <0x01bc0000 0x2440000>;
			};
		};
	};
};

&rwdt {
	timeout-sec = <60>;
	status = "okay";
};

&scif0 {
	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif_clk {
	clock-frequency = <14745600>;
};