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git01.mediatek.com / filogic / uboot / 8ba3d406324aae2d9a3a94febfcf7ff94fcd722b / . / arch / arm / dts / imx8mm-venice-gw7902.dts
blob: adf521632d63a774c7495bda6052179b929eebcb [file] [log] [blame]
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2021 Gateworks Corporation
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/linux-event-codes.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/net/ti-dp83867.h>
12
13#include "imx8mm.dtsi"
14
15/ {
16 model = "Gateworks Venice GW7902 i.MX8MM board";
17 compatible = "gw,imx8mm-gw7902", "fsl,imx8mm";
18
19 aliases {
20 usb0 = &usbotg1;
21 usb1 = &usbotg2;
22 };
23
24 chosen {
25 stdout-path = &uart2;
26 };
27
28 memory@40000000 {
29 device_type = "memory";
30 reg = <0x0 0x40000000 0 0x80000000>;
31 };
32
33 can20m: can20m {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <20000000>;
37 clock-output-names = "can20m";
38 };
39
40 gpio-keys {
41 compatible = "gpio-keys";
42
43 user-pb {
44 label = "user_pb";
45 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
46 linux,code = <BTN_0>;
47 };
48
49 user-pb1x {
50 label = "user_pb1x";
51 linux,code = <BTN_1>;
52 interrupt-parent = <&gsc>;
53 interrupts = <0>;
54 };
55
56 key-erased {
57 label = "key_erased";
58 linux,code = <BTN_2>;
59 interrupt-parent = <&gsc>;
60 interrupts = <1>;
61 };
62
63 eeprom-wp {
64 label = "eeprom_wp";
65 linux,code = <BTN_3>;
66 interrupt-parent = <&gsc>;
67 interrupts = <2>;
68 };
69
70 tamper {
71 label = "tamper";
72 linux,code = <BTN_4>;
73 interrupt-parent = <&gsc>;
74 interrupts = <5>;
75 };
76
77 switch-hold {
78 label = "switch_hold";
79 linux,code = <BTN_5>;
80 interrupt-parent = <&gsc>;
81 interrupts = <7>;
82 };
83 };
84
85 led-controller {
86 compatible = "gpio-leds";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_gpio_leds>;
89
90 led-0 {
91 function = LED_FUNCTION_STATUS;
92 color = <LED_COLOR_ID_GREEN>;
93 label = "panel1";
94 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
95 default-state = "off";
96 };
97
98 led-1 {
99 function = LED_FUNCTION_STATUS;
100 color = <LED_COLOR_ID_GREEN>;
101 label = "panel2";
102 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
103 default-state = "off";
104 };
105
106 led-2 {
107 function = LED_FUNCTION_STATUS;
108 color = <LED_COLOR_ID_GREEN>;
109 label = "panel3";
110 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
111 default-state = "off";
112 };
113
114 led-3 {
115 function = LED_FUNCTION_STATUS;
116 color = <LED_COLOR_ID_GREEN>;
117 label = "panel4";
118 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
119 default-state = "off";
120 };
121
122 led-4 {
123 function = LED_FUNCTION_STATUS;
124 color = <LED_COLOR_ID_GREEN>;
125 label = "panel5";
126 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
127 default-state = "off";
128 };
129 };
130
131 pps {
132 compatible = "pps-gpio";
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_pps>;
135 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
136 status = "okay";
137 };
138
139 reg_3p3v: regulator-3p3v {
140 compatible = "regulator-fixed";
141 regulator-name = "3P3V";
142 regulator-min-microvolt = <3300000>;
143 regulator-max-microvolt = <3300000>;
144 };
145
146 reg_usb1_vbus: regulator-usb1 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_reg_usb1>;
149 compatible = "regulator-fixed";
150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152 enable-active-high;
153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <5000000>;
155 };
156
157 reg_wifi: regulator-wifi {
158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_reg_wl>;
160 compatible = "regulator-fixed";
161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high;
164 startup-delay-us = <100>;
165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <3300000>;
167 };
168};
169
170&A53_0 {
171 cpu-supply = <&buck2>;
172};
173
174&A53_1 {
175 cpu-supply = <&buck2>;
176};
177
178&A53_2 {
179 cpu-supply = <&buck2>;
180};
181
182&A53_3 {
183 cpu-supply = <&buck2>;
184};
185
186&ddrc {
187 operating-points-v2 = <&ddrc_opp_table>;
188
189 ddrc_opp_table: opp-table {
190 compatible = "operating-points-v2";
191
192 opp-25M {
193 opp-hz = /bits/ 64 <25000000>;
194 };
195
196 opp-100M {
197 opp-hz = /bits/ 64 <100000000>;
198 };
199
200 opp-750M {
201 opp-hz = /bits/ 64 <750000000>;
202 };
203 };
204};
205
206&ecspi1 {
207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210 status = "okay";
211
212 can@0 {
213 compatible = "microchip,mcp2515";
214 reg = <0>;
215 clocks = <&can20m>;
216 oscillator-frequency = <20000000>;
217 interrupt-parent = <&gpio2>;
218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
219 spi-max-frequency = <10000000>;
220 };
221};
222
223/* off-board header */
224&ecspi2 {
225 pinctrl-names = "default";
226 pinctrl-0 = <&pinctrl_spi2>;
227 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
228 status = "okay";
229};
230
231&fec1 {
232 pinctrl-names = "default";
233 pinctrl-0 = <&pinctrl_fec1>;
234 phy-mode = "rgmii-id";
235 phy-handle = <&ethphy0>;
236 local-mac-address = [00 00 00 00 00 00];
237 status = "okay";
238
239 mdio {
240 #address-cells = <1>;
241 #size-cells = <0>;
242
243 ethphy0: ethernet-phy@0 {
244 compatible = "ethernet-phy-ieee802.3-c22";
245 reg = <0>;
246 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
247 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
248 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
249 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
250 };
251 };
252};
253
254&i2c1 {
255 clock-frequency = <100000>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_i2c1>;
258 status = "okay";
259
260 gsc: gsc@20 {
261 compatible = "gw,gsc";
262 reg = <0x20>;
263 pinctrl-0 = <&pinctrl_gsc>;
264 interrupt-parent = <&gpio2>;
265 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
266 interrupt-controller;
267 #interrupt-cells = <1>;
268
269 adc {
270 compatible = "gw,gsc-adc";
271 #address-cells = <1>;
272 #size-cells = <0>;
273
274 channel@6 {
275 gw,mode = <0>;
276 reg = <0x06>;
277 label = "temp";
278 };
279
280 channel@8 {
281 gw,mode = <1>;
282 reg = <0x08>;
283 label = "vdd_bat";
284 };
285
286 channel@82 {
287 gw,mode = <2>;
288 reg = <0x82>;
289 label = "vin";
290 gw,voltage-divider-ohms = <22100 1000>;
291 gw,voltage-offset-microvolt = <700000>;
292 };
293
294 channel@84 {
295 gw,mode = <2>;
296 reg = <0x84>;
297 label = "vin_4p0";
298 gw,voltage-divider-ohms = <10000 10000>;
299 };
300
301 channel@86 {
302 gw,mode = <2>;
303 reg = <0x86>;
304 label = "vdd_3p3";
305 gw,voltage-divider-ohms = <10000 10000>;
306 };
307
308 channel@88 {
309 gw,mode = <2>;
310 reg = <0x88>;
311 label = "vdd_0p9";
312 };
313
314 channel@8c {
315 gw,mode = <2>;
316 reg = <0x8c>;
317 label = "vdd_soc";
318 };
319
320 channel@8e {
321 gw,mode = <2>;
322 reg = <0x8e>;
323 label = "vdd_arm";
324 };
325
326 channel@90 {
327 gw,mode = <2>;
328 reg = <0x90>;
329 label = "vdd_1p8";
330 };
331
332 channel@92 {
333 gw,mode = <2>;
334 reg = <0x92>;
335 label = "vdd_dram";
336 };
337
338 channel@98 {
339 gw,mode = <2>;
340 reg = <0x98>;
341 label = "vdd_1p0";
342 };
343
344 channel@9a {
345 gw,mode = <2>;
346 reg = <0x9a>;
347 label = "vdd_2p5";
348 gw,voltage-divider-ohms = <10000 10000>;
349 };
350
Tim Harveyf6d4bc42022-03-08 10:44:43 -0800[diff] [blame]351 channel@9c {
352 gw,mode = <2>;
353 reg = <0x9c>;
354 label = "vdd_5p0";
355 gw,voltage-divider-ohms = <10000 10000>;
356 };
357
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]358 channel@a2 {
359 gw,mode = <2>;
360 reg = <0xa2>;
361 label = "vdd_gsc";
362 gw,voltage-divider-ohms = <10000 10000>;
363 };
364 };
365 };
366
367 gpio: gpio@23 {
368 compatible = "nxp,pca9555";
369 reg = <0x23>;
370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-parent = <&gsc>;
373 interrupts = <4>;
374 };
375
376 pmic@4b {
377 compatible = "rohm,bd71847";
378 reg = <0x4b>;
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_pmic>;
381 interrupt-parent = <&gpio3>;
382 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
383 rohm,reset-snvs-powered;
384 #clock-cells = <0>;
385 clocks = <&osc_32k 0>;
386 clock-output-names = "clk-32k-out";
387
388 regulators {
389 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
390 BUCK1 {
391 regulator-name = "buck1";
392 regulator-min-microvolt = <700000>;
393 regulator-max-microvolt = <1300000>;
394 regulator-boot-on;
395 regulator-always-on;
396 regulator-ramp-delay = <1250>;
397 };
398
399 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
400 buck2: BUCK2 {
401 regulator-name = "buck2";
402 regulator-min-microvolt = <700000>;
403 regulator-max-microvolt = <1300000>;
404 regulator-boot-on;
405 regulator-always-on;
406 regulator-ramp-delay = <1250>;
407 rohm,dvs-run-voltage = <1000000>;
408 rohm,dvs-idle-voltage = <900000>;
409 };
410
411 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
412 BUCK3 {
413 regulator-name = "buck3";
414 regulator-min-microvolt = <700000>;
415 regulator-max-microvolt = <1350000>;
416 regulator-boot-on;
417 regulator-always-on;
418 };
419
420 /* vdd_3p3 */
421 BUCK4 {
422 regulator-name = "buck4";
423 regulator-min-microvolt = <3000000>;
424 regulator-max-microvolt = <3300000>;
425 regulator-boot-on;
426 regulator-always-on;
427 };
428
429 /* vdd_1p8 */
430 BUCK5 {
431 regulator-name = "buck5";
432 regulator-min-microvolt = <1605000>;
433 regulator-max-microvolt = <1995000>;
434 regulator-boot-on;
435 regulator-always-on;
436 };
437
438 /* vdd_dram */
439 BUCK6 {
440 regulator-name = "buck6";
441 regulator-min-microvolt = <800000>;
442 regulator-max-microvolt = <1400000>;
443 regulator-boot-on;
444 regulator-always-on;
445 };
446
447 /* nvcc_snvs_1p8 */
448 LDO1 {
449 regulator-name = "ldo1";
450 regulator-min-microvolt = <1600000>;
451 regulator-max-microvolt = <1900000>;
452 regulator-boot-on;
453 regulator-always-on;
454 };
455
456 /* vdd_snvs_0p8 */
457 LDO2 {
458 regulator-name = "ldo2";
459 regulator-min-microvolt = <800000>;
460 regulator-max-microvolt = <900000>;
461 regulator-boot-on;
462 regulator-always-on;
463 };
464
465 /* vdda_1p8 */
466 LDO3 {
467 regulator-name = "ldo3";
468 regulator-min-microvolt = <1800000>;
469 regulator-max-microvolt = <3300000>;
470 regulator-boot-on;
471 regulator-always-on;
472 };
473
474 LDO4 {
475 regulator-name = "ldo4";
476 regulator-min-microvolt = <900000>;
477 regulator-max-microvolt = <1800000>;
478 regulator-boot-on;
479 regulator-always-on;
480 };
481
482 LDO6 {
483 regulator-name = "ldo6";
484 regulator-min-microvolt = <900000>;
485 regulator-max-microvolt = <1800000>;
486 regulator-boot-on;
487 regulator-always-on;
488 };
489 };
490 };
491
492 eeprom@50 {
493 compatible = "atmel,24c02";
494 reg = <0x50>;
495 pagesize = <16>;
496 };
497
498 eeprom@51 {
499 compatible = "atmel,24c02";
500 reg = <0x51>;
501 pagesize = <16>;
502 };
503
504 eeprom@52 {
505 compatible = "atmel,24c02";
506 reg = <0x52>;
507 pagesize = <16>;
508 };
509
510 eeprom@53 {
511 compatible = "atmel,24c02";
512 reg = <0x53>;
513 pagesize = <16>;
514 };
515
516 rtc@68 {
517 compatible = "dallas,ds1672";
518 reg = <0x68>;
519 };
520};
521
522&i2c2 {
523 clock-frequency = <400000>;
524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_i2c2>;
526 status = "okay";
527
528 accelerometer@19 {
529 pinctrl-names = "default";
530 pinctrl-0 = <&pinctrl_accel>;
531 compatible = "st,lis2de12";
532 reg = <0x19>;
533 st,drdy-int-pin = <1>;
534 interrupt-parent = <&gpio1>;
535 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
536 interrupt-names = "INT1";
537 };
538
539 secure-element@60 {
540 compatible = "nxp,se050";
541 reg = <0x60>;
542 };
543};
544
545/* off-board header */
546&i2c3 {
547 clock-frequency = <400000>;
548 pinctrl-names = "default";
549 pinctrl-0 = <&pinctrl_i2c3>;
550 status = "okay";
551};
552
553/* off-board header */
554&i2c4 {
555 clock-frequency = <400000>;
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_i2c4>;
558 status = "okay";
559};
560
561/* off-board header */
562&sai3 {
563 pinctrl-names = "default";
564 pinctrl-0 = <&pinctrl_sai3>;
565 assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
566 assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
567 assigned-clock-rates = <24576000>;
568 status = "okay";
569};
570
571/* RS232/RS485/RS422 selectable */
572&uart1 {
573 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
575 rts-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
576 cts-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
577 status = "okay";
578};
579
580/* RS232 console */
581&uart2 {
582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_uart2>;
584 status = "okay";
585};
586
587/* bluetooth HCI */
588&uart3 {
589 pinctrl-names = "default";
590 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
591 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
592 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
593 status = "okay";
594
595 bluetooth {
596 compatible = "brcm,bcm4330-bt";
597 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
598 };
599};
600
601/* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
602&uart4 {
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_uart4>;
605 rts-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
606 cts-gpios = <&gpio4 1 GPIO_ACTIVE_LOW>;
607 dtr-gpios = <&gpio4 3 GPIO_ACTIVE_LOW>;
608 dsr-gpios = <&gpio4 4 GPIO_ACTIVE_LOW>;
609 dcd-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
610 status = "okay";
611};
612
613&usbotg1 {
614 dr_mode = "host";
615 vbus-supply = <&reg_usb1_vbus>;
616 disable-over-current;
617 status = "okay";
618};
619
620&usbotg2 {
621 dr_mode = "host";
622 disable-over-current;
623 status = "okay";
624};
625
626/* SDIO WiFi */
627&usdhc2 {
628 pinctrl-names = "default";
629 pinctrl-0 = <&pinctrl_usdhc2>;
630 bus-width = <4>;
631 non-removable;
632 vmmc-supply = <&reg_wifi>;
633 status = "okay";
634};
635
636/* eMMC */
637&usdhc3 {
638 pinctrl-names = "default", "state_100mhz", "state_200mhz";
639 pinctrl-0 = <&pinctrl_usdhc3>;
640 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
641 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
642 bus-width = <8>;
643 non-removable;
644 status = "okay";
645};
646
647&wdog1 {
648 pinctrl-names = "default";
649 pinctrl-0 = <&pinctrl_wdog>;
650 fsl,ext-reset-output;
651 status = "okay";
652};
653
654&iomuxc {
655 pinctrl-names = "default";
656 pinctrl-0 = <&pinctrl_hog>;
657
658 pinctrl_hog: hoggrp {
659 fsl,pins = <
660 MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
Tim Harveyb94a3812021-10-06 13:13:23 -0700[diff] [blame]661 MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
Tim Harvey6603b5e2021-07-27 15:19:41 -0700[diff] [blame]662 MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
663 MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
664 MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x40000041 /* AMP GPIO1 */
665 MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x40000041 /* AMP GPIO2 */
666 MX8MM_IOMUXC_SAI1_TXC_GPIO4_IO11 0x40000041 /* AMP GPIO3 */
667 MX8MM_IOMUXC_SAI1_MCLK_GPIO4_IO20 0x40000041 /* AMP_GPIO4 */
668 MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
669 MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
670 MX8MM_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
671 MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
672 MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
673 MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
674 MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
675 >;
676 };
677
678 pinctrl_accel: accelgrp {
679 fsl,pins = <
680 MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
681 >;
682 };
683
684 pinctrl_fec1: fec1grp {
685 fsl,pins = <
686 MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
687 MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
688 MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
689 MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
690 MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
691 MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
692 MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
693 MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
694 MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
695 MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
696 MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
697 MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
698 MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
699 MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
700 MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
701 MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
702 MX8MM_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
703 MX8MM_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
704 >;
705 };
706
707 pinctrl_gsc: gscgrp {
708 fsl,pins = <
709 MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
710 >;
711 };
712
713 pinctrl_i2c1: i2c1grp {
714 fsl,pins = <
715 MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
716 MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
717 >;
718 };
719
720 pinctrl_i2c2: i2c2grp {
721 fsl,pins = <
722 MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
723 MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
724 >;
725 };
726
727 pinctrl_i2c3: i2c3grp {
728 fsl,pins = <
729 MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
730 MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
731 >;
732 };
733
734 pinctrl_i2c4: i2c4grp {
735 fsl,pins = <
736 MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
737 MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
738 >;
739 };
740
741 pinctrl_gpio_leds: gpioledgrp {
742 fsl,pins = <
743 MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x40000019
744 MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x40000019
745 MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x40000019
746 MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x40000019
747 MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x40000019
748 >;
749 };
750
751 pinctrl_pmic: pmicgrp {
752 fsl,pins = <
753 MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
754 >;
755 };
756
757 pinctrl_pps: ppsgrp {
758 fsl,pins = <
759 MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
760 >;
761 };
762
763 pinctrl_reg_wl: regwlgrp {
764 fsl,pins = <
765 MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
766 >;
767 };
768
769 pinctrl_reg_usb1: regusb1grp {
770 fsl,pins = <
771 MX8MM_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
772 >;
773 };
774
775 pinctrl_sai3: sai3grp {
776 fsl,pins = <
777 MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
778 MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
779 MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
780 MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
781 MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
782 >;
783 };
784
785 pinctrl_spi1: spi1grp {
786 fsl,pins = <
787 MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
788 MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
789 MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
790 MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
791 MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
792 >;
793 };
794
795 pinctrl_spi2: spi2grp {
796 fsl,pins = <
797 MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
798 MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
799 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
800 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
801 >;
802 };
803
804 pinctrl_uart1: uart1grp {
805 fsl,pins = <
806 MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
807 MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
808 MX8MM_IOMUXC_SAI1_TXFS_GPIO4_IO10 0x140 /* RTS */
809 MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x140 /* CTS */
810 >;
811 };
812
813 pinctrl_uart1_gpio: uart1gpiogrp {
814 fsl,pins = <
815 MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
816 MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
817 MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
818 >;
819 };
820
821 pinctrl_uart2: uart2grp {
822 fsl,pins = <
823 MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
824 MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
825 >;
826 };
827
828 pinctrl_uart3_gpio: uart3_gpiogrp {
829 fsl,pins = <
830 MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
831 >;
832 };
833
834 pinctrl_uart3: uart3grp {
835 fsl,pins = <
836 MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
837 MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
838 MX8MM_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
839 MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
840 >;
841 };
842
843 pinctrl_uart4: uart4grp {
844 fsl,pins = <
845 MX8MM_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
846 MX8MM_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
847 MX8MM_IOMUXC_SAI1_RXC_GPIO4_IO1 0x140 /* CTS */
848 MX8MM_IOMUXC_SAI1_RXD0_GPIO4_IO2 0x140 /* RTS */
849 MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x140 /* DTR */
850 MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x140 /* DSR */
851 MX8MM_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x140 /* DCD */
852 MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x140 /* RI */
853 MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x140 /* GNSS_PPS */
854 MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
855 >;
856 };
857
858 pinctrl_usdhc2: usdhc2grp {
859 fsl,pins = <
860 MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
861 MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
862 MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
863 MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
864 MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
865 MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
866 >;
867 };
868
869 pinctrl_usdhc3: usdhc3grp {
870 fsl,pins = <
871 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
872 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
873 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
874 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
875 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
876 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
877 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
878 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
879 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
880 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
881 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
882 >;
883 };
884
885 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
886 fsl,pins = <
887 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
888 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
889 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
890 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
891 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
892 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
893 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
894 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
895 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
896 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
897 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
898 >;
899 };
900
901 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
902 fsl,pins = <
903 MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
904 MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
905 MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
906 MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
907 MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
908 MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
909 MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
910 MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
911 MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
912 MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
913 MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
914 >;
915 };
916
917 pinctrl_wdog: wdoggrp {
918 fsl,pins = <
919 MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
920 >;
921 };
922};