blob: 408862bef04294ed9787164b68b0fdee5e2adf6d [file] [log] [blame]
Ezequiel Garcia00eb01a2018-01-12 12:33:50 -03001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Bitmain Antminer S9 board DTS
4 *
5 * Copyright (C) 2018 Michal Simek
6 * Copyright (C) 2018 VanguardiaSur
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
12 model = "Bitmain Antminer S9 Board";
13 compatible = "bitmain,antminer-s9", "xlnx,zynq-7000";
14
15 aliases {
16 ethernet0 = &gem0;
17 serial0 = &uart1;
18 mmc0 = &sdhci0;
19 gpio0 = &gpio0;
20 };
21
22 memory@0 {
23 device_type = "memory";
24 reg = <0x0 0x40000000>;
25 };
26
27 reserved-memory {
28 #address-cells = <1>;
29 #size-cells = <1>;
30 ranges;
31
32 bootcount@efffff0 {
33 reg = <0xefffff0 0x10>;
34 no-map;
35 };
36
37 fpga_space@f000000 {
38 reg = <0xf000000 0x1000000>;
39 no-map;
40 };
41 };
42
43 chosen {
44 bootargs = "earlycon";
45 stdout-path = "serial0:115200n8";
46 };
47};
48
49&clkc {
50 ps-clk-frequency = <33333333>;
51};
52
Michael Walle42abea62022-02-23 15:10:34 +010053&nfc0 {
Michal Simek1ad97712021-03-18 16:04:44 +010054 status = "okay";
55};
56
57&smcc {
58 status = "okay";
59};
60
Ezequiel Garcia00eb01a2018-01-12 12:33:50 -030061&gem0 {
62 status = "okay";
63 phy-mode = "rgmii-id";
64 phy-handle = <&ethernet_phy>;
65
66 /* 0362/5e62 */
67 ethernet_phy: ethernet-phy@1 {
68 reg = <1>;
69 };
70};
71
72&sdhci0 {
73 u-boot,dm-pre-reloc;
74 status = "okay";
75 disable-wp;
76};
77
78&uart1 {
79 u-boot,dm-pre-reloc;
80 status = "okay";
81};
82
83&watchdog0 {
84 reset-on-timeout;
85 timeout-sec = <200>;
86};