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git01.mediatek.com / filogic / uboot / 8b92bdf8bbe7f5640137bf21597a588b81dc691c / . / arch / x86 / include / asm / mtrr.h
blob: fda4eae10d8f1262a67ed46aae5e6656b679bba2 [file] [log] [blame]
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]1/*
2 * Copyright (c) 2014 Google, Inc
3 *
4 * From Coreboot file of the same name
5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8
9#ifndef _ASM_MTRR_H
10#define _ASM_MTRR_H
11
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]12/* MTRR region types */
13#define MTRR_TYPE_UNCACHEABLE 0
14#define MTRR_TYPE_WRCOMB 1
15#define MTRR_TYPE_WRTHROUGH 4
16#define MTRR_TYPE_WRPROT 5
17#define MTRR_TYPE_WRBACK 6
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]18
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]19#define MTRR_TYPE_COUNT 7
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]20
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]21#define MTRR_CAP_MSR 0x0fe
22#define MTRR_DEF_TYPE_MSR 0x2ff
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]23
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]24#define MTRR_DEF_TYPE_EN (1 << 11)
25#define MTRR_DEF_TYPE_FIX_EN (1 << 10)
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]26
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]27#define MTRR_PHYS_BASE_MSR(reg) (0x200 + 2 * (reg))
28#define MTRR_PHYS_MASK_MSR(reg) (0x200 + 2 * (reg) + 1)
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]29
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]30#define MTRR_PHYS_MASK_VALID (1 << 11)
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]31
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]32#define MTRR_BASE_TYPE_MASK 0x7
33
34/* Number of MTRRs supported */
35#define MTRR_COUNT 8
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]36
37#if !defined(__ASSEMBLER__)
38
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]39/**
40 * Information about the previous MTRR state, set up by mtrr_open()
41 *
42 * @deftype: Previous value of MTRR_DEF_TYPE_MSR
43 * @enable_cache: true if cache was enabled
44 */
45struct mtrr_state {
46 uint64_t deftype;
47 bool enable_cache;
48};
49
50/**
51 * mtrr_open() - Prepare to adjust MTRRs
52 *
53 * Use mtrr_open() passing in a structure - this function will init it. Then
54 * when done, pass the same structure to mtrr_close() to re-enable MTRRs and
55 * possibly the cache.
56 *
57 * @state: Empty structure to pass in to hold settings
58 */
59void mtrr_open(struct mtrr_state *state);
60
61/**
62 * mtrr_open() - Clean up after adjusting MTRRs, and enable them
63 *
64 * This uses the structure containing information returned from mtrr_open().
65 *
66 * @state: Structure from mtrr_open()
67 */
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]68void mtrr_close(struct mtrr_state *state);
69
70/**
71 * mtrr_add_request() - Add a new MTRR request
72 *
73 * This adds a request for a memory region to be set up in a particular way.
74 *
75 * @type: Requested type (MTRR_TYPE_)
76 * @start: Start address
77 * @size: Size
Bin Meng80d29762015-01-22 11:29:41 +0800[diff] [blame]78 *
79 * @return: 0 on success, non-zero on failure
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]80 */
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]81int mtrr_add_request(int type, uint64_t start, uint64_t size);
82
83/**
84 * mtrr_commit() - set up the MTRR registers based on current requests
85 *
86 * This sets up MTRRs for the available DRAM and the requests received so far.
87 * It must be called with caches disabled.
88 *
89 * @do_caches: true if caches are currently on
Bin Meng80d29762015-01-22 11:29:41 +0800[diff] [blame]90 *
91 * @return: 0 on success, non-zero on failure
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]92 */
Simon Glass7bf5b9e2015-01-01 16:18:07 -0700[diff] [blame]93int mtrr_commit(bool do_caches);
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]94
95#endif
96
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]97#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
98# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
99#endif
100
101#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
102# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
103#endif
104
105#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
106
Simon Glass98f139b2014-11-12 22:42:10 -0700[diff] [blame]107#endif