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git01.mediatek.com / filogic / uboot / 8b5ea658994ac88224296703f19b9ac2e9a07760 / . / board / ti / ks2_evm / board_k2e.c
blob: 43dfc48a53da2085f699450c698dd34af2d71163 [file] [log] [blame]
Hao Zhang82be0132014-07-16 00:59:27 +0300[diff] [blame]1/*
2 * K2E EVM : Board initialization
3 *
4 * (C) Copyright 2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#include <common.h>
11#include <asm/arch/ddr3.h>
12#include <asm/arch/hardware.h>
Hao Zhang6d4ec892014-10-17 21:01:17 +0300[diff] [blame]13#include <asm/ti-common/keystone_net.h>
Hao Zhang82be0132014-07-16 00:59:27 +0300[diff] [blame]14
15DECLARE_GLOBAL_DATA_PTR;
16
17unsigned int external_clk[ext_clk_count] = {
18 [sys_clk] = 100000000,
19 [alt_core_clk] = 100000000,
20 [pa_clk] = 100000000,
21 [ddr3_clk] = 100000000,
22 [mcm_clk] = 312500000,
23 [pcie_clk] = 100000000,
24 [sgmii_clk] = 156250000,
25 [xgmii_clk] = 156250000,
26 [usb_clk] = 100000000,
27};
28
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300[diff] [blame]29static struct pll_init_data core_pll_config[] = {
30 CORE_PLL_800,
31 CORE_PLL_850,
32 CORE_PLL_1000,
33 CORE_PLL_1250,
34 CORE_PLL_1350,
35 CORE_PLL_1400,
36 CORE_PLL_1500,
Hao Zhang82be0132014-07-16 00:59:27 +0300[diff] [blame]37};
38
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300[diff] [blame]39static struct pll_init_data pa_pll_config =
40 PASS_PLL_1000;
41
Hao Zhang6d4ec892014-10-17 21:01:17 +0300[diff] [blame]42#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
43struct eth_priv_t eth_priv_cfg[] = {
44 {
45 .int_name = "K2E_EMAC0",
46 .rx_flow = 0,
47 .phy_addr = 0,
48 .slave_port = 1,
49 .sgmii_link_type = SGMII_LINK_MAC_PHY,
50 },
51 {
52 .int_name = "K2E_EMAC1",
53 .rx_flow = 8,
54 .phy_addr = 1,
55 .slave_port = 2,
56 .sgmii_link_type = SGMII_LINK_MAC_PHY,
57 },
58 {
59 .int_name = "K2E_EMAC2",
60 .rx_flow = 16,
61 .phy_addr = 2,
62 .slave_port = 3,
63 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
64 },
65 {
66 .int_name = "K2E_EMAC3",
67 .rx_flow = 24,
68 .phy_addr = 3,
69 .slave_port = 4,
70 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
71 },
72 {
73 .int_name = "K2E_EMAC4",
74 .rx_flow = 32,
75 .phy_addr = 4,
76 .slave_port = 5,
77 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
78 },
79 {
80 .int_name = "K2E_EMAC5",
81 .rx_flow = 40,
82 .phy_addr = 5,
83 .slave_port = 6,
84 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
85 },
86 {
87 .int_name = "K2E_EMAC6",
88 .rx_flow = 48,
89 .phy_addr = 6,
90 .slave_port = 7,
91 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
92 },
93 {
94 .int_name = "K2E_EMAC7",
95 .rx_flow = 56,
96 .phy_addr = 7,
97 .slave_port = 8,
98 .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
99 },
100};
101
102int get_num_eth_ports(void)
103{
104 return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
105}
106#endif
107
Hao Zhang82be0132014-07-16 00:59:27 +0300[diff] [blame]108#if defined(CONFIG_BOARD_EARLY_INIT_F)
109int board_early_init_f(void)
110{
Vitaly Andrianov047e7802014-07-25 22:23:19 +0300[diff] [blame]111 int speed;
112
113 speed = get_max_dev_speed();
114 init_pll(&core_pll_config[speed]);
115
116 init_pll(&pa_pll_config);
117
Hao Zhang82be0132014-07-16 00:59:27 +0300[diff] [blame]118 return 0;
119}
120#endif
Hao Zhang95948202014-10-22 16:32:31 +0300[diff] [blame]121
122#ifdef CONFIG_SPL_BUILD
123static struct pll_init_data spl_pll_config[] = {
124 CORE_PLL_800,
125};
126
127void spl_init_keystone_plls(void)
128{
129 init_plls(ARRAY_SIZE(spl_pll_config), spl_pll_config);
130}
131#endif