blob: d0a740dd3f40492a776211c5c550178d1f377331 [file] [log] [blame]
Alifer Moraesa0a29482020-03-06 07:46:33 -03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2020 NXP
4 */
5
6#include <common.h>
7#include <env.h>
8#include <init.h>
9#include <malloc.h>
10#include <errno.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060011#include <asm/global_data.h>
Alifer Moraesa0a29482020-03-06 07:46:33 -030012#include <asm/io.h>
13#include <miiphy.h>
14#include <netdev.h>
15#include <asm/mach-imx/iomux-v3.h>
16#include <asm-generic/gpio.h>
17#include <fsl_esdhc_imx.h>
18#include <mmc.h>
19#include <asm/arch/imx8mq_pins.h>
20#include <asm/arch/sys_proto.h>
21#include <asm/mach-imx/gpio.h>
22#include <asm/arch/clock.h>
23#include <spl.h>
24
25DECLARE_GLOBAL_DATA_PTR;
26
27#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
28
29#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
30
31static iomux_v3_cfg_t const wdog_pads[] = {
32 IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
33};
34
35static iomux_v3_cfg_t const uart_pads[] = {
36 IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
37 IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
38};
39
40int board_early_init_f(void)
41{
42 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
43
44 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
45 set_wdog_reset(wdog);
46
47 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
48
49 return 0;
50}
51
Alifer Moraesa0a29482020-03-06 07:46:33 -030052#ifdef CONFIG_FEC_MXC
53static int setup_fec(void)
54{
55 struct iomuxc_gpr_base_regs *gpr =
56 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
57
58 /* Use 125M anatop REF_CLK1 for ENET1, not from external */
59 clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
60 return set_clk_enet(ENET_125MHZ);
61}
62
63int board_phy_config(struct phy_device *phydev)
64{
65 /* enable rgmii rxc skew and phy mode select to RGMII copper */
66 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
67 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
68
69 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
70 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
71
72 if (phydev->drv->config)
73 phydev->drv->config(phydev);
74 return 0;
75}
76#endif
77
78int board_init(void)
79{
80#ifdef CONFIG_FEC_MXC
81 setup_fec();
82#endif
83
84 return 0;
85}
86
87int board_mmc_get_env_dev(int devno)
88{
89 return devno;
90}