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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jon Loeligerd68e2ba2006-05-30 17:47:00 -05002/*
Timur Tabi7ba8b322010-03-31 17:44:13 -05003 * Copyright 2006,2010 Freescale Semiconductor
Jon Loeligerd68e2ba2006-05-30 17:47:00 -05004 * Jeff Brown
5 * Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -05006 */
7
8#include <common.h>
Jon Loeligerd68e2ba2006-05-30 17:47:00 -05009#include <command.h>
Andy Flemingdb2b5bd2008-08-31 16:33:30 -050010#include <asm/io.h>
Jon Loeliger4eab6232008-01-15 13:42:41 -060011
Timur Tabi7ba8b322010-03-31 17:44:13 -050012#define pixis_base (u8 *)PIXIS_BASE
Haiying Wang57b6e9c2007-01-22 12:37:30 -060013
14/*
15 * Simple board reset.
16 */
17void pixis_reset(void)
18{
Kumar Gala146c4b22009-07-22 10:12:39 -050019 out_8(pixis_base + PIXIS_RST, 0);
Haiying Wang57b6e9c2007-01-22 12:37:30 -060020
Timur Tabi7ba8b322010-03-31 17:44:13 -050021 while (1);
22}
Haiying Wang57b6e9c2007-01-22 12:37:30 -060023
Jon Loeligerd68e2ba2006-05-30 17:47:00 -050024/*
25 * Per table 27, page 58 of MPC8641HPCN spec.
26 */
Timur Tabi7ba8b322010-03-31 17:44:13 -050027static int set_px_sysclk(unsigned long sysclk)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -050028{
29 u8 sysclk_s, sysclk_r, sysclk_v, vclkh, vclkl, sysclk_aux;
30
31 switch (sysclk) {
32 case 33:
33 sysclk_s = 0x04;
34 sysclk_r = 0x04;
35 sysclk_v = 0x07;
36 sysclk_aux = 0x00;
37 break;
38 case 40:
39 sysclk_s = 0x01;
40 sysclk_r = 0x1F;
41 sysclk_v = 0x20;
42 sysclk_aux = 0x01;
43 break;
44 case 50:
45 sysclk_s = 0x01;
46 sysclk_r = 0x1F;
47 sysclk_v = 0x2A;
48 sysclk_aux = 0x02;
49 break;
50 case 66:
51 sysclk_s = 0x01;
52 sysclk_r = 0x04;
53 sysclk_v = 0x04;
54 sysclk_aux = 0x03;
55 break;
56 case 83:
57 sysclk_s = 0x01;
58 sysclk_r = 0x1F;
59 sysclk_v = 0x4B;
60 sysclk_aux = 0x04;
61 break;
62 case 100:
63 sysclk_s = 0x01;
64 sysclk_r = 0x1F;
65 sysclk_v = 0x5C;
66 sysclk_aux = 0x05;
67 break;
68 case 134:
69 sysclk_s = 0x06;
70 sysclk_r = 0x1F;
71 sysclk_v = 0x3B;
72 sysclk_aux = 0x06;
73 break;
74 case 166:
75 sysclk_s = 0x06;
76 sysclk_r = 0x1F;
77 sysclk_v = 0x4B;
78 sysclk_aux = 0x07;
79 break;
80 default:
81 printf("Unsupported SYSCLK frequency.\n");
82 return 0;
83 }
84
Jon Loeliger4fbb09c2006-08-22 12:25:27 -050085 vclkh = (sysclk_s << 5) | sysclk_r;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -050086 vclkl = sysclk_v;
87
Kumar Gala146c4b22009-07-22 10:12:39 -050088 out_8(pixis_base + PIXIS_VCLKH, vclkh);
89 out_8(pixis_base + PIXIS_VCLKL, vclkl);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -050090
Kumar Gala146c4b22009-07-22 10:12:39 -050091 out_8(pixis_base + PIXIS_AUX, sysclk_aux);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -050092
93 return 1;
94}
95
Timur Tabi7ba8b322010-03-31 17:44:13 -050096/* Set the CFG_SYSPLL bits
97 *
98 * This only has effect if PX_VCFGEN0[SYSPLL]=1, which is true if
99 * read_from_px_regs() is called.
100 */
101static int set_px_mpxpll(unsigned long mpxpll)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500102{
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500103 switch (mpxpll) {
104 case 2:
105 case 4:
106 case 6:
107 case 8:
108 case 10:
109 case 12:
110 case 14:
111 case 16:
Timur Tabi7ba8b322010-03-31 17:44:13 -0500112 clrsetbits_8(pixis_base + PIXIS_VSPEED1, 0x1F, mpxpll);
113 return 1;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500114 }
115
Timur Tabi7ba8b322010-03-31 17:44:13 -0500116 printf("Unsupported MPXPLL ratio.\n");
117 return 0;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500118}
119
Timur Tabi7ba8b322010-03-31 17:44:13 -0500120static int set_px_corepll(unsigned long corepll)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500121{
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500122 u8 val;
123
Timur Tabi7ba8b322010-03-31 17:44:13 -0500124 switch (corepll) {
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500125 case 20:
126 val = 0x08;
127 break;
128 case 25:
129 val = 0x0C;
130 break;
131 case 30:
132 val = 0x10;
133 break;
134 case 35:
135 val = 0x1C;
136 break;
137 case 40:
138 val = 0x14;
139 break;
140 case 45:
141 val = 0x0E;
142 break;
143 default:
144 printf("Unsupported COREPLL ratio.\n");
145 return 0;
146 }
147
Timur Tabi7ba8b322010-03-31 17:44:13 -0500148 clrsetbits_8(pixis_base + PIXIS_VSPEED0, 0x1F, val);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500149 return 1;
150}
151
Timur Tabi7ba8b322010-03-31 17:44:13 -0500152#ifndef CONFIG_SYS_PIXIS_VCFGEN0_ENABLE
153#define CONFIG_SYS_PIXIS_VCFGEN0_ENABLE 0x1C
154#endif
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500155
Timur Tabi7ba8b322010-03-31 17:44:13 -0500156/* Tell the PIXIS where to find the COREPLL, MPXPLL, SYSCLK values
157 *
158 * The PIXIS can be programmed to look at either the on-board dip switches
159 * or various other PIXIS registers to determine the values for COREPLL,
160 * MPXPLL, and SYSCLK.
161 *
162 * CONFIG_SYS_PIXIS_VCFGEN0_ENABLE is the value to write to the PIXIS_VCFGEN0
163 * register that tells the pixis to use the various PIXIS register.
164 */
165static void read_from_px_regs(int set)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500166{
Kumar Gala146c4b22009-07-22 10:12:39 -0500167 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN0);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500168
169 if (set)
Timur Tabi7ba8b322010-03-31 17:44:13 -0500170 tmp = tmp | CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500171 else
Timur Tabi7ba8b322010-03-31 17:44:13 -0500172 tmp = tmp & ~CONFIG_SYS_PIXIS_VCFGEN0_ENABLE;
173
Kumar Gala146c4b22009-07-22 10:12:39 -0500174 out_8(pixis_base + PIXIS_VCFGEN0, tmp);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500175}
176
Timur Tabi7ba8b322010-03-31 17:44:13 -0500177/* CONFIG_SYS_PIXIS_VBOOT_ENABLE is the value to write to the PX_VCFGEN1
178 * register that tells the pixis to use the PX_VBOOT[LBMAP] register.
179 */
180#ifndef CONFIG_SYS_PIXIS_VBOOT_ENABLE
181#define CONFIG_SYS_PIXIS_VBOOT_ENABLE 0x04
182#endif
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500183
Timur Tabi7ba8b322010-03-31 17:44:13 -0500184/* Configure the source of the boot location
185 *
186 * The PIXIS can be programmed to look at either the on-board dip switches
187 * or the PX_VBOOT[LBMAP] register to determine where we should boot.
188 *
189 * If we want to boot from the alternate boot bank, we need to tell the PIXIS
190 * to ignore the on-board dip switches and use the PX_VBOOT[LBMAP] instead.
191 */
192static void read_from_px_regs_altbank(int set)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500193{
Kumar Gala146c4b22009-07-22 10:12:39 -0500194 u8 tmp = in_8(pixis_base + PIXIS_VCFGEN1);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500195
196 if (set)
Timur Tabi7ba8b322010-03-31 17:44:13 -0500197 tmp = tmp | CONFIG_SYS_PIXIS_VBOOT_ENABLE;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500198 else
Timur Tabi7ba8b322010-03-31 17:44:13 -0500199 tmp = tmp & ~CONFIG_SYS_PIXIS_VBOOT_ENABLE;
200
Kumar Gala146c4b22009-07-22 10:12:39 -0500201 out_8(pixis_base + PIXIS_VCFGEN1, tmp);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500202}
203
Timur Tabi7ba8b322010-03-31 17:44:13 -0500204/* CONFIG_SYS_PIXIS_VBOOT_MASK contains the bits to set in VBOOT register that
205 * tells the PIXIS what the alternate flash bank is.
206 *
207 * Note that it's not really a mask. It contains the actual LBMAP bits that
208 * must be set to select the alternate bank. This code assumes that the
209 * primary bank has these bits set to 0, and the alternate bank has these
210 * bits set to 1.
211 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200212#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
213#define CONFIG_SYS_PIXIS_VBOOT_MASK (0x40)
Jason Jinf08899a2007-10-29 19:26:21 +0800214#endif
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500215
Timur Tabi7ba8b322010-03-31 17:44:13 -0500216/* Tell the PIXIS to boot from the default flash bank
217 *
218 * Program the default flash bank into the VBOOT register. This register is
219 * used only if PX_VCFGEN1[FLASH]=1.
220 */
221static void clear_altbank(void)
James Yang61f17812008-01-16 11:58:08 -0600222{
Timur Tabi7ba8b322010-03-31 17:44:13 -0500223 clrbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
James Yang61f17812008-01-16 11:58:08 -0600224}
225
Timur Tabi7ba8b322010-03-31 17:44:13 -0500226/* Tell the PIXIS to boot from the alternate flash bank
227 *
228 * Program the alternate flash bank into the VBOOT register. This register is
229 * used only if PX_VCFGEN1[FLASH]=1.
230 */
231static void set_altbank(void)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500232{
Timur Tabi7ba8b322010-03-31 17:44:13 -0500233 setbits_8(pixis_base + PIXIS_VBOOT, CONFIG_SYS_PIXIS_VBOOT_MASK);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500234}
235
Timur Tabi7ba8b322010-03-31 17:44:13 -0500236/* Reset the board with watchdog disabled.
237 *
238 * This respects the altbank setting.
239 */
240static void set_px_go(void)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500241{
Timur Tabi7ba8b322010-03-31 17:44:13 -0500242 /* Disable the VELA sequencer and watchdog */
243 clrbits_8(pixis_base + PIXIS_VCTL, 9);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500244
Timur Tabi7ba8b322010-03-31 17:44:13 -0500245 /* Reboot by starting the VELA sequencer */
246 setbits_8(pixis_base + PIXIS_VCTL, 0x1);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500247
Timur Tabi7ba8b322010-03-31 17:44:13 -0500248 while (1);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500249}
250
Timur Tabi7ba8b322010-03-31 17:44:13 -0500251/* Reset the board with watchdog enabled.
252 *
253 * This respects the altbank setting.
254 */
255static void set_px_go_with_watchdog(void)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500256{
Timur Tabi7ba8b322010-03-31 17:44:13 -0500257 /* Disable the VELA sequencer */
258 clrbits_8(pixis_base + PIXIS_VCTL, 1);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500259
Timur Tabi7ba8b322010-03-31 17:44:13 -0500260 /* Enable the watchdog and reboot by starting the VELA sequencer */
261 setbits_8(pixis_base + PIXIS_VCTL, 0x9);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500262
Timur Tabi7ba8b322010-03-31 17:44:13 -0500263 while (1);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500264}
265
Timur Tabi7ba8b322010-03-31 17:44:13 -0500266/* Disable the watchdog
267 *
268 */
Simon Glassed38aef2020-05-10 11:40:03 -0600269static int pixis_disable_watchdog_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
270 char *const argv[])
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500271{
Timur Tabi7ba8b322010-03-31 17:44:13 -0500272 /* Disable the VELA sequencer and the watchdog */
273 clrbits_8(pixis_base + PIXIS_VCTL, 9);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500274
275 return 0;
276}
277
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500278U_BOOT_CMD(
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200279 diswd, 1, 0, pixis_disable_watchdog_cmd,
280 "Disable watchdog timer",
281 ""
282);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500283
Liu Yu46269062008-10-10 11:40:58 +0800284#ifdef CONFIG_PIXIS_SGMII_CMD
Timur Tabi7ba8b322010-03-31 17:44:13 -0500285
286/* Enable or disable SGMII mode for a TSEC
287 */
Simon Glassed38aef2020-05-10 11:40:03 -0600288static int pixis_set_sgmii(struct cmd_tbl *cmdtp, int flag, int argc,
289 char *const argv[])
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500290{
291 int which_tsec = -1;
Timur Tabi7ba8b322010-03-31 17:44:13 -0500292 unsigned char mask;
293 unsigned char switch_mask;
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500294
Timur Tabi7ba8b322010-03-31 17:44:13 -0500295 if ((argc > 2) && (strcmp(argv[1], "all") != 0))
296 which_tsec = simple_strtoul(argv[1], NULL, 0);
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500297
298 switch (which_tsec) {
Liu Yu46269062008-10-10 11:40:58 +0800299#ifdef CONFIG_TSEC1
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500300 case 1:
301 mask = PIXIS_VSPEED2_TSEC1SER;
302 switch_mask = PIXIS_VCFGEN1_TSEC1SER;
303 break;
Liu Yu46269062008-10-10 11:40:58 +0800304#endif
305#ifdef CONFIG_TSEC2
306 case 2:
307 mask = PIXIS_VSPEED2_TSEC2SER;
308 switch_mask = PIXIS_VCFGEN1_TSEC2SER;
309 break;
310#endif
311#ifdef CONFIG_TSEC3
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500312 case 3:
313 mask = PIXIS_VSPEED2_TSEC3SER;
314 switch_mask = PIXIS_VCFGEN1_TSEC3SER;
315 break;
Liu Yu46269062008-10-10 11:40:58 +0800316#endif
317#ifdef CONFIG_TSEC4
318 case 4:
319 mask = PIXIS_VSPEED2_TSEC4SER;
320 switch_mask = PIXIS_VCFGEN1_TSEC4SER;
321 break;
322#endif
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500323 default:
Liu Yu46269062008-10-10 11:40:58 +0800324 mask = PIXIS_VSPEED2_MASK;
325 switch_mask = PIXIS_VCFGEN1_MASK;
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500326 break;
327 }
328
329 /* Toggle whether the switches or FPGA control the settings */
330 if (!strcmp(argv[argc - 1], "switch"))
Kumar Gala146c4b22009-07-22 10:12:39 -0500331 clrbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500332 else
Kumar Gala146c4b22009-07-22 10:12:39 -0500333 setbits_8(pixis_base + PIXIS_VCFGEN1, switch_mask);
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500334
335 /* If it's not the switches, enable or disable SGMII, as specified */
336 if (!strcmp(argv[argc - 1], "on"))
Kumar Gala146c4b22009-07-22 10:12:39 -0500337 clrbits_8(pixis_base + PIXIS_VSPEED2, mask);
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500338 else if (!strcmp(argv[argc - 1], "off"))
Kumar Gala146c4b22009-07-22 10:12:39 -0500339 setbits_8(pixis_base + PIXIS_VSPEED2, mask);
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500340
341 return 0;
342}
343
344U_BOOT_CMD(
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200345 pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
346 "pixis_set_sgmii"
347 " - Enable or disable SGMII mode for a given TSEC \n",
348 "\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
349 " TSEC num: 1,2,3,4 or 'all'. 'all' is default.\n"
350 " on - enables SGMII\n"
351 " off - disables SGMII\n"
352 " switch - use switch settings"
353);
Timur Tabi7ba8b322010-03-31 17:44:13 -0500354
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500355#endif
356
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500357/*
358 * This function takes the non-integral cpu:mpx pll ratio
359 * and converts it to an integer that can be used to assign
360 * FPGA register values.
361 * input: strptr i.e. argv[2]
362 */
Timur Tabi7ba8b322010-03-31 17:44:13 -0500363static unsigned long strfractoint(char *strptr)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500364{
Timur Tabi7ba8b322010-03-31 17:44:13 -0500365 int i, j;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500366 int mulconst;
Kumar Gala85e44122011-11-09 10:02:11 -0600367 int no_dec = 0;
Timur Tabi7ba8b322010-03-31 17:44:13 -0500368 unsigned long intval = 0, decval = 0;
369 char intarr[3], decarr[3];
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500370
371 /* Assign the integer part to intarr[]
372 * If there is no decimal point i.e.
373 * if the ratio is an integral value
374 * simply create the intarr.
375 */
376 i = 0;
James Yang61f17812008-01-16 11:58:08 -0600377 while (strptr[i] != '.') {
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500378 if (strptr[i] == 0) {
379 no_dec = 1;
380 break;
381 }
382 intarr[i] = strptr[i];
383 i++;
384 }
385
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500386 intarr[i] = '\0';
387
388 if (no_dec) {
389 /* Currently needed only for single digit corepll ratios */
Jon Loeliger4fbb09c2006-08-22 12:25:27 -0500390 mulconst = 10;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500391 decval = 0;
392 } else {
393 j = 0;
Jon Loeliger4fbb09c2006-08-22 12:25:27 -0500394 i++; /* Skipping the decimal point */
James Yang61f17812008-01-16 11:58:08 -0600395 while ((strptr[i] >= '0') && (strptr[i] <= '9')) {
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500396 decarr[j] = strptr[i];
397 i++;
398 j++;
399 }
400
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500401 decarr[j] = '\0';
402
403 mulconst = 1;
Timur Tabi7ba8b322010-03-31 17:44:13 -0500404 for (i = 0; i < j; i++)
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500405 mulconst *= 10;
Simon Glassff9b9032021-07-24 09:03:30 -0600406 decval = dectoul(decarr, NULL);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500407 }
408
Simon Glassff9b9032021-07-24 09:03:30 -0600409 intval = dectoul(intarr, NULL);
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500410 intval = intval * mulconst;
411
Timur Tabi7ba8b322010-03-31 17:44:13 -0500412 return intval + decval;
Jon Loeligerd68e2ba2006-05-30 17:47:00 -0500413}
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600414
Simon Glassed38aef2020-05-10 11:40:03 -0600415static int pixis_reset_cmd(struct cmd_tbl *cmdtp, int flag, int argc,
416 char *const argv[])
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600417{
James Yang61f17812008-01-16 11:58:08 -0600418 unsigned int i;
419 char *p_cf = NULL;
420 char *p_cf_sysclk = NULL;
421 char *p_cf_corepll = NULL;
422 char *p_cf_mpxpll = NULL;
423 char *p_altbank = NULL;
424 char *p_wd = NULL;
Timur Tabi7ba8b322010-03-31 17:44:13 -0500425 int unknown_param = 0;
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600426
427 /*
428 * No args is a simple reset request.
429 */
430 if (argc <= 1) {
431 pixis_reset();
432 /* not reached */
433 }
434
James Yang61f17812008-01-16 11:58:08 -0600435 for (i = 1; i < argc; i++) {
436 if (strcmp(argv[i], "cf") == 0) {
437 p_cf = argv[i];
438 if (i + 3 >= argc) {
439 break;
440 }
441 p_cf_sysclk = argv[i+1];
442 p_cf_corepll = argv[i+2];
443 p_cf_mpxpll = argv[i+3];
444 i += 3;
445 continue;
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600446 }
447
James Yang61f17812008-01-16 11:58:08 -0600448 if (strcmp(argv[i], "altbank") == 0) {
449 p_altbank = argv[i];
450 continue;
451 }
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600452
James Yang61f17812008-01-16 11:58:08 -0600453 if (strcmp(argv[i], "wd") == 0) {
454 p_wd = argv[i];
455 continue;
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600456 }
457
James Yang61f17812008-01-16 11:58:08 -0600458 unknown_param = 1;
459 }
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600460
James Yang61f17812008-01-16 11:58:08 -0600461 /*
462 * Check that cf has all required parms
463 */
464 if ((p_cf && !(p_cf_sysclk && p_cf_corepll && p_cf_mpxpll))
Wolfgang Denka1be4762008-05-20 16:00:29 +0200465 || unknown_param) {
Ed Swarthout06c70d62008-10-08 23:38:01 -0500466#ifdef CONFIG_SYS_LONGHELP
James Yang61f17812008-01-16 11:58:08 -0600467 puts(cmdtp->help);
York Sun13444b22013-05-31 08:48:04 -0700468 putc('\n');
Ed Swarthout06c70d62008-10-08 23:38:01 -0500469#endif
James Yang61f17812008-01-16 11:58:08 -0600470 return 1;
471 }
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600472
James Yang61f17812008-01-16 11:58:08 -0600473 /*
474 * PIXIS seems to be sensitive to the ordering of
475 * the registers that are touched.
476 */
477 read_from_px_regs(0);
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600478
Timur Tabi7ba8b322010-03-31 17:44:13 -0500479 if (p_altbank)
James Yang61f17812008-01-16 11:58:08 -0600480 read_from_px_regs_altbank(0);
Timur Tabi7ba8b322010-03-31 17:44:13 -0500481
James Yang61f17812008-01-16 11:58:08 -0600482 clear_altbank();
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600483
James Yang61f17812008-01-16 11:58:08 -0600484 /*
485 * Clock configuration specified.
486 */
487 if (p_cf) {
488 unsigned long sysclk;
489 unsigned long corepll;
490 unsigned long mpxpll;
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600491
Simon Glassff9b9032021-07-24 09:03:30 -0600492 sysclk = dectoul(p_cf_sysclk, NULL);
Timur Tabi7ba8b322010-03-31 17:44:13 -0500493 corepll = strfractoint(p_cf_corepll);
Simon Glassff9b9032021-07-24 09:03:30 -0600494 mpxpll = dectoul(p_cf_mpxpll, NULL);
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600495
James Yang61f17812008-01-16 11:58:08 -0600496 if (!(set_px_sysclk(sysclk)
497 && set_px_corepll(corepll)
498 && set_px_mpxpll(mpxpll))) {
Ed Swarthout06c70d62008-10-08 23:38:01 -0500499#ifdef CONFIG_SYS_LONGHELP
James Yang61f17812008-01-16 11:58:08 -0600500 puts(cmdtp->help);
York Sun13444b22013-05-31 08:48:04 -0700501 putc('\n');
Ed Swarthout06c70d62008-10-08 23:38:01 -0500502#endif
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600503 return 1;
504 }
James Yang61f17812008-01-16 11:58:08 -0600505 read_from_px_regs(1);
506 }
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600507
James Yang61f17812008-01-16 11:58:08 -0600508 /*
509 * Altbank specified
510 *
511 * NOTE CHANGE IN BEHAVIOR: previous code would default
512 * to enabling watchdog if altbank is specified.
513 * Now the watchdog must be enabled explicitly using 'wd'.
514 */
515 if (p_altbank) {
516 set_altbank();
517 read_from_px_regs_altbank(1);
518 }
519
520 /*
521 * Reset with watchdog specified.
522 */
Timur Tabi7ba8b322010-03-31 17:44:13 -0500523 if (p_wd)
James Yang61f17812008-01-16 11:58:08 -0600524 set_px_go_with_watchdog();
Timur Tabi7ba8b322010-03-31 17:44:13 -0500525 else
James Yang61f17812008-01-16 11:58:08 -0600526 set_px_go();
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600527
James Yang61f17812008-01-16 11:58:08 -0600528 /*
529 * Shouldn't be reached.
530 */
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600531 return 0;
532}
533
534
535U_BOOT_CMD(
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200536 pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
Peter Tyserdfb72b82009-01-27 18:03:12 -0600537 "Reset the board using the FPGA sequencer",
Haiying Wang57b6e9c2007-01-22 12:37:30 -0600538 " pixis_reset\n"
539 " pixis_reset [altbank]\n"
540 " pixis_reset altbank wd\n"
541 " pixis_reset altbank cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>\n"
Wolfgang Denkc54781c2009-05-24 17:06:54 +0200542 " pixis_reset cf <SYSCLK freq> <COREPLL ratio> <MPXPLL ratio>"
543);