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Mike Frysinger66c4cf42008-02-04 19:26:55 -05001/*
2 * File: include/asm-blackfin/mach-bf537/anomaly.h
3 * Bugs: Enter bugs at http://blackfin.uclinux.org/
4 *
Mike Frysingerd4bf13a2009-02-18 12:51:31 -05005 * Copyright (C) 2004-2009 Analog Devices Inc.
Mike Frysinger66c4cf42008-02-04 19:26:55 -05006 * Licensed under the GPL-2 or later.
7 */
8
Mike Frysinger8b416b32009-04-04 08:22:36 -04009/* This file should be up to date with:
Mike Frysinger21797192008-10-06 03:45:55 -040010 * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
Mike Frysinger66c4cf42008-02-04 19:26:55 -050011 */
12
13#ifndef _MACH_ANOMALY_H_
14#define _MACH_ANOMALY_H_
15
16/* We do not support 0.1 silicon - sorry */
17#if __SILICON_REVISION__ < 2
18# error will not work on BF537 silicon version 0.0 or 0.1
19#endif
20
21#if defined(__ADSPBF534__)
22# define ANOMALY_BF534 1
23#else
24# define ANOMALY_BF534 0
25#endif
26#if defined(__ADSPBF536__)
27# define ANOMALY_BF536 1
28#else
29# define ANOMALY_BF536 0
30#endif
31#if defined(__ADSPBF537__)
32# define ANOMALY_BF537 1
33#else
34# define ANOMALY_BF537 0
35#endif
36
37/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
38#define ANOMALY_05000074 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -040039/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050040#define ANOMALY_05000119 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -040041/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050042#define ANOMALY_05000122 (1)
43/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
44#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
Mike Frysinger8b416b32009-04-04 08:22:36 -040045/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050046#define ANOMALY_05000180 (1)
47/* Instruction Cache Is Not Functional */
48#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
Mike Frysinger8b416b32009-04-04 08:22:36 -040049/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050050#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040051/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050052#define ANOMALY_05000245 (1)
53/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
54#define ANOMALY_05000247 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -040055/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050056#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
57/* EMAC Tx DMA error after an early frame abort */
58#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040059/* Maximum External Clock Speed for Timers */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050060#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040061/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050062#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
Mike Frysinger8b416b32009-04-04 08:22:36 -040063/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050064#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
65/* EMAC MDIO input latched on wrong MDC edge */
66#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040067/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050068#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040069/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050070#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
Mike Frysinger8b416b32009-04-04 08:22:36 -040071/* ICPLB_STATUS MMR Register May Be Corrupted */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050072#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
Mike Frysinger8b416b32009-04-04 08:22:36 -040073/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050074#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040075/* Stores To Data Cache May Be Lost */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050076#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040077/* Hardware Loop Corrupted When Taking an ICPLB Exception */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050078#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
Mike Frysinger8b416b32009-04-04 08:22:36 -040079/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050080#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040081/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050082#define ANOMALY_05000265 (1)
83/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
84#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040085/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050086#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040087/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050088#define ANOMALY_05000272 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -040089/* Writes to Synchronous SDRAM Memory May Be Lost */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050090#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040091/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050092#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040093/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050094#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
95/* SPI Master boot mode does not work well with Atmel Data flash devices */
96#define ANOMALY_05000280 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -040097/* False Hardware Error Exception When ISR Context Is Not Restored */
Mike Frysinger66c4cf42008-02-04 19:26:55 -050098#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -040099/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500100#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
101/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
102#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
103/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
104#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400105/* SPORTs May Receive Bad Data If FIFOs Fill Up */
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500106#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400107/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500108#define ANOMALY_05000301 (1)
109/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
110#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
Mike Frysingerd4bf13a2009-02-18 12:51:31 -0500111/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500112#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
113/* SCKELOW Bit Does Not Maintain State Through Hibernate */
114#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
115/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
116#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400117/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500118#define ANOMALY_05000310 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400119/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500120#define ANOMALY_05000312 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400121/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500122#define ANOMALY_05000313 (1)
123/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
124#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
125/* EMAC RMII mode: collisions occur in Full Duplex mode */
126#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
127/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
128#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
129/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
130#define ANOMALY_05000322 (1)
131/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
132#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
Mike Frysinger5e857882008-08-07 13:09:50 -0400133/* New Feature: UART Remains Enabled after UART Boot */
134#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
135/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
136#define ANOMALY_05000355 (1)
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500137/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
138#define ANOMALY_05000357 (1)
139/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
140#define ANOMALY_05000359 (1)
Mike Frysinger5e857882008-08-07 13:09:50 -0400141/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
142#define ANOMALY_05000366 (1)
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500143/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
144#define ANOMALY_05000371 (1)
Mike Frysinger5e857882008-08-07 13:09:50 -0400145/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
146#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
147/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
148#define ANOMALY_05000403 (1)
Mike Frysinger21797192008-10-06 03:45:55 -0400149/* Speculative Fetches Can Cause Undesired External FIFO Operations */
150#define ANOMALY_05000416 (1)
151/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
152#define ANOMALY_05000425 (1)
153/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
154#define ANOMALY_05000426 (1)
155/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
156#define ANOMALY_05000443 (1)
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500157
158/* Anomalies that don't exist on this proc */
159#define ANOMALY_05000125 (0)
160#define ANOMALY_05000158 (0)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400161#define ANOMALY_05000171 (0)
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500162#define ANOMALY_05000183 (0)
163#define ANOMALY_05000198 (0)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400164#define ANOMALY_05000227 (0)
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500165#define ANOMALY_05000230 (0)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400166#define ANOMALY_05000242 (0)
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500167#define ANOMALY_05000266 (0)
168#define ANOMALY_05000311 (0)
169#define ANOMALY_05000323 (0)
Mike Frysinger5e857882008-08-07 13:09:50 -0400170#define ANOMALY_05000353 (1)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400171#define ANOMALY_05000362 (1)
Mike Frysinger5e857882008-08-07 13:09:50 -0400172#define ANOMALY_05000363 (0)
Mike Frysingerd4bf13a2009-02-18 12:51:31 -0500173#define ANOMALY_05000380 (0)
Mike Frysinger21797192008-10-06 03:45:55 -0400174#define ANOMALY_05000386 (1)
175#define ANOMALY_05000412 (0)
Mike Frysinger8b416b32009-04-04 08:22:36 -0400176#define ANOMALY_05000430 (0)
Mike Frysinger21797192008-10-06 03:45:55 -0400177#define ANOMALY_05000432 (0)
178#define ANOMALY_05000435 (0)
Mike Frysingerd4bf13a2009-02-18 12:51:31 -0500179#define ANOMALY_05000447 (0)
180#define ANOMALY_05000448 (0)
Mike Frysinger66c4cf42008-02-04 19:26:55 -0500181
182#endif