Marek Vasut | 78687b7 | 2011-11-08 23:18:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com> |
| 3 | * on behalf of DENX Software Engineering GmbH |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or |
| 6 | * modify it under the terms of the GNU General Public License as |
| 7 | * published by the Free Software Foundation; either version 2 of |
| 8 | * the License, or (at your option) any later version. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 18 | * MA 02111-1307 USA |
| 19 | */ |
| 20 | #ifndef __M28_H__ |
| 21 | #define __M28_H__ |
| 22 | |
| 23 | #include <asm/arch/regs-base.h> |
| 24 | |
| 25 | /* |
| 26 | * SoC configurations |
| 27 | */ |
| 28 | #define CONFIG_MX28 /* i.MX28 SoC */ |
| 29 | #define CONFIG_MXS_GPIO /* GPIO control */ |
| 30 | #define CONFIG_SYS_HZ 1000 /* Ticks per second */ |
| 31 | |
| 32 | /* |
| 33 | * Define M28EVK machine type by hand until it lands in mach-types |
| 34 | */ |
| 35 | #define MACH_TYPE_M28EVK 3613 |
| 36 | |
| 37 | #define CONFIG_MACH_TYPE MACH_TYPE_M28EVK |
| 38 | |
| 39 | #define CONFIG_SYS_NO_FLASH |
| 40 | #define CONFIG_SYS_ICACHE_OFF |
| 41 | #define CONFIG_SYS_DCACHE_OFF |
| 42 | #define CONFIG_BOARD_EARLY_INIT_F |
| 43 | #define CONFIG_ARCH_CPU_INIT |
| 44 | |
| 45 | /* |
Marek Vasut | 926227e | 2011-11-08 23:18:21 +0000 | [diff] [blame] | 46 | * SPL |
| 47 | */ |
| 48 | #define CONFIG_SPL |
| 49 | #define CONFIG_SPL_NO_CPU_SUPPORT_CODE |
| 50 | #define CONFIG_SPL_START_S_PATH "board/denx/m28evk" |
| 51 | #define CONFIG_SPL_LDSCRIPT "board/denx/m28evk/u-boot-spl.lds" |
| 52 | |
| 53 | /* |
Marek Vasut | 78687b7 | 2011-11-08 23:18:20 +0000 | [diff] [blame] | 54 | * U-Boot Commands |
| 55 | */ |
| 56 | #include <config_cmd_default.h> |
| 57 | #define CONFIG_DISPLAY_CPUINFO |
| 58 | #define CONFIG_DOS_PARTITION |
| 59 | |
| 60 | #define CONFIG_CMD_CACHE |
| 61 | #define CONFIG_CMD_DATE |
| 62 | #define CONFIG_CMD_DHCP |
| 63 | #define CONFIG_CMD_EEPROM |
| 64 | #define CONFIG_CMD_EXT2 |
| 65 | #define CONFIG_CMD_FAT |
| 66 | #define CONFIG_CMD_GPIO |
| 67 | #define CONFIG_CMD_I2C |
| 68 | #define CONFIG_CMD_MII |
| 69 | #define CONFIG_CMD_MMC |
| 70 | #define CONFIG_CMD_NAND |
| 71 | #define CONFIG_CMD_NET |
| 72 | #define CONFIG_CMD_NFS |
| 73 | #define CONFIG_CMD_PING |
| 74 | #define CONFIG_CMD_SETEXPR |
| 75 | #define CONFIG_CMD_SF |
| 76 | #define CONFIG_CMD_SPI |
| 77 | |
| 78 | /* |
| 79 | * Memory configurations |
| 80 | */ |
| 81 | #define CONFIG_NR_DRAM_BANKS 1 /* 2 banks of DRAM */ |
| 82 | #define PHYS_SDRAM_1 0x40000000 /* Base address */ |
| 83 | #define PHYS_SDRAM_1_SIZE 0x08000000 /* 128 MB */ |
| 84 | #define CONFIG_STACKSIZE 0x00010000 /* 128 KB stack */ |
| 85 | #define CONFIG_SYS_MALLOC_LEN 0x00400000 /* 4 MB for malloc */ |
| 86 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* Initial data */ |
| 87 | #define CONFIG_SYS_MEMTEST_START 0x40000000 /* Memtest start adr */ |
| 88 | #define CONFIG_SYS_MEMTEST_END 0x40400000 /* 4 MB RAM test */ |
| 89 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 90 | /* Point initial SP in SRAM so SPL can use it too. */ |
| 91 | #define CONFIG_SYS_INIT_SP_ADDR 0x00002000 |
| 92 | /* |
| 93 | * We need to sacrifice first 4 bytes of RAM here to avoid triggering some |
| 94 | * strange BUG in ROM corrupting first 4 bytes of RAM when loading U-Boot |
| 95 | * binary. In case there was more of this mess, 0x100 bytes are skipped. |
| 96 | */ |
| 97 | #define CONFIG_SYS_TEXT_BASE 0x40000100 |
| 98 | |
| 99 | /* |
| 100 | * U-Boot general configurations |
| 101 | */ |
| 102 | #define CONFIG_SYS_LONGHELP |
| 103 | #define CONFIG_SYS_PROMPT "=> " |
| 104 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
| 105 | #define CONFIG_SYS_PBSIZE \ |
| 106 | (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
| 107 | /* Print buffer size */ |
| 108 | #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ |
| 109 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 110 | /* Boot argument buffer size */ |
| 111 | #define CONFIG_VERSION_VARIABLE /* U-BOOT version */ |
| 112 | #define CONFIG_AUTO_COMPLETE /* Command auto complete */ |
| 113 | #define CONFIG_CMDLINE_EDITING /* Command history etc */ |
| 114 | #define CONFIG_SYS_HUSH_PARSER |
| 115 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " |
| 116 | |
| 117 | /* |
| 118 | * Serial Driver |
| 119 | */ |
| 120 | #define CONFIG_PL011_SERIAL |
| 121 | #define CONFIG_PL011_CLOCK 24000000 |
| 122 | #define CONFIG_PL01x_PORTS { (void *)MXS_UARTDBG_BASE } |
| 123 | #define CONFIG_CONS_INDEX 0 |
| 124 | #define CONFIG_BAUDRATE 115200 /* Default baud rate */ |
| 125 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 126 | |
| 127 | /* |
| 128 | * MMC Driver |
| 129 | */ |
| 130 | #ifdef CONFIG_CMD_MMC |
| 131 | #define CONFIG_MMC |
| 132 | #define CONFIG_GENERIC_MMC |
| 133 | #define CONFIG_MXS_MMC |
| 134 | #endif |
| 135 | |
| 136 | /* |
| 137 | * NAND |
| 138 | */ |
| 139 | #ifdef CONFIG_CMD_NAND |
| 140 | #define CONFIG_NAND_MXS |
| 141 | #define CONFIG_APBH_DMA |
| 142 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 143 | #define CONFIG_SYS_NAND_BASE 0x60000000 |
| 144 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 145 | #define NAND_MAX_CHIPS 8 |
| 146 | |
| 147 | /* Environment is in NAND */ |
| 148 | #define CONFIG_ENV_IS_IN_NAND |
| 149 | #define CONFIG_ENV_SIZE (16 * 1024) |
| 150 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE |
| 151 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
| 152 | #define CONFIG_ENV_RANGE (512 * 1024) |
| 153 | #define CONFIG_ENV_OFFSET 0x300000 |
| 154 | #define CONFIG_ENV_OFFSET_REDUND \ |
| 155 | (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE) |
| 156 | |
| 157 | #define CONFIG_CMD_UBI |
| 158 | #define CONFIG_CMD_UBIFS |
| 159 | #define CONFIG_CMD_MTDPARTS |
| 160 | #define CONFIG_RBTREE |
| 161 | #define CONFIG_LZO |
| 162 | #define CONFIG_MTD_DEVICE |
| 163 | #define CONFIG_MTD_PARTITIONS |
| 164 | #define MTDIDS_DEFAULT "nand0=gpmi-nand.0" |
| 165 | #define MTDPARTS_DEFAULT \ |
| 166 | "mtdparts=gpmi-nand.0:" \ |
| 167 | "3m(bootloader)ro," \ |
| 168 | "512k(environment)," \ |
| 169 | "512k(redundant-environment)," \ |
| 170 | "4m(kernel)," \ |
| 171 | "-(filesystem)" |
| 172 | #endif |
| 173 | |
| 174 | /* |
| 175 | * Ethernet on SOC (FEC) |
| 176 | */ |
| 177 | #ifdef CONFIG_CMD_NET |
| 178 | #define CONFIG_NET_MULTI |
| 179 | #define CONFIG_ETHPRIME "FEC0" |
| 180 | #define CONFIG_FEC_MXC |
| 181 | #define CONFIG_FEC_MXC_MULTI |
| 182 | #define CONFIG_MII |
| 183 | #define CONFIG_DISCOVER_PHY |
| 184 | #define CONFIG_FEC_XCV_TYPE RMII |
| 185 | #endif |
| 186 | |
| 187 | /* |
| 188 | * I2C |
| 189 | */ |
| 190 | #ifdef CONFIG_CMD_I2C |
| 191 | #define CONFIG_I2C_MXS |
| 192 | #define CONFIG_HARD_I2C |
| 193 | #define CONFIG_SYS_I2C_SPEED 400000 |
| 194 | #endif |
| 195 | |
| 196 | /* |
| 197 | * EEPROM |
| 198 | */ |
| 199 | #ifdef CONFIG_CMD_EEPROM |
| 200 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
| 201 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 |
| 202 | #endif |
| 203 | |
| 204 | /* |
| 205 | * RTC |
| 206 | */ |
| 207 | #ifdef CONFIG_CMD_DATE |
| 208 | /* Use the internal RTC in the MXS chip */ |
| 209 | #define CONFIG_RTC_INTERNAL |
| 210 | #ifdef CONFIG_RTC_INTERNAL |
| 211 | #define CONFIG_RTC_MXS |
| 212 | #else |
| 213 | #define CONFIG_RTC_M41T62 |
| 214 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
| 215 | #define CONFIG_SYS_M41T11_BASE_YEAR 2000 |
| 216 | #endif |
| 217 | #endif |
| 218 | |
| 219 | /* |
| 220 | * SPI |
| 221 | */ |
| 222 | #ifdef CONFIG_CMD_SPI |
| 223 | #define CONFIG_HARD_SPI |
| 224 | #define CONFIG_MXS_SPI |
| 225 | #define CONFIG_SPI_HALF_DUPLEX |
| 226 | #define CONFIG_DEFAULT_SPI_BUS 2 |
| 227 | #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 |
| 228 | |
| 229 | /* SPI FLASH */ |
| 230 | #ifdef CONFIG_CMD_SF |
| 231 | #define CONFIG_SPI_FLASH |
| 232 | #define CONFIG_SPI_FLASH_STMICRO |
| 233 | #define CONFIG_SPI_FLASH_CS 2 |
| 234 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 |
| 235 | #define CONFIG_SF_DEFAULT_SPEED 24000000 |
| 236 | |
| 237 | #define CONFIG_ENV_SPI_CS 0 |
| 238 | #define CONFIG_ENV_SPI_BUS 2 |
| 239 | #define CONFIG_ENV_SPI_MAX_HZ 24000000 |
| 240 | #define CONFIG_ENV_SPI_MODE SPI_MODE_0 |
| 241 | #endif |
| 242 | #endif |
| 243 | |
| 244 | /* |
| 245 | * Boot Linux |
| 246 | */ |
| 247 | #define CONFIG_CMDLINE_TAG |
| 248 | #define CONFIG_SETUP_MEMORY_TAGS |
| 249 | #define CONFIG_BOOTDELAY 3 |
| 250 | #define CONFIG_BOOTFILE "uImage" |
| 251 | #define CONFIG_BOOTARGS "console=ttyAM0,115200n8 " |
| 252 | #define CONFIG_BOOTCOMMAND "run bootcmd_net" |
| 253 | #define CONFIG_LOADADDR 0x42000000 |
| 254 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
| 255 | |
| 256 | /* |
| 257 | * Extra Environments |
| 258 | */ |
| 259 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 260 | "update_nand_full_filename=u-boot.nand\0" \ |
| 261 | "update_nand_firmware_filename=u-boot.sb\0" \ |
| 262 | "update_nand_firmware_maxsz=0x100000\0" \ |
| 263 | "update_nand_stride=0x40\0" /* MX28 datasheet ch. 12.12 */ \ |
| 264 | "update_nand_count=0x4\0" /* MX28 datasheet ch. 12.12 */ \ |
| 265 | "update_nand_get_fcb_size=" /* Get size of FCB blocks */ \ |
| 266 | "nand device 0 ; " \ |
| 267 | "nand info ; " \ |
| 268 | "setexpr fcb_sz ${update_nand_stride} * ${update_nand_count};" \ |
| 269 | "setexpr update_nand_fcb ${fcb_sz} * ${nand_writesize}\0" \ |
| 270 | "update_nand_full=" /* Update FCB, DBBT and FW */ \ |
| 271 | "if tftp ${update_nand_full_filename} ; then " \ |
| 272 | "run update_nand_get_fcb_size ; " \ |
| 273 | "nand scrub -y 0x0 ${filesize} ; " \ |
| 274 | "nand write.raw ${loadaddr} 0x0 ${update_nand_fcb} ; " \ |
| 275 | "setexpr update_off ${loadaddr} + ${update_nand_fcb} ; " \ |
| 276 | "setexpr update_sz ${filesize} - ${update_nand_fcb} ; " \ |
| 277 | "nand write ${update_off} ${update_nand_fcb} ${update_sz} ; " \ |
| 278 | "fi\0" \ |
| 279 | "update_nand_firmware=" /* Update only firmware */ \ |
| 280 | "if tftp ${update_nand_firmware_filename} ; then " \ |
| 281 | "run update_nand_get_fcb_size ; " \ |
| 282 | "setexpr fcb_sz ${update_nand_fcb} * 2 ; " /* FCB + DBBT */ \ |
| 283 | "setexpr fw_sz ${update_nand_firmware_maxsz} * 2 ; " \ |
| 284 | "setexpr fw_off ${fcb_sz} + ${update_nand_firmware_maxsz};" \ |
| 285 | "nand erase ${fcb_sz} ${fw_sz} ; " \ |
| 286 | "nand write ${loadaddr} ${fcb_sz} ${filesize} ; " \ |
| 287 | "nand write ${loadaddr} ${fw_off} ${filesize} ; " \ |
| 288 | "fi\0" |
| 289 | |
| 290 | #endif /* __M28_H__ */ |