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Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
4 * Jean-Jacques Hiblot <jjhiblot@ti.com>
5 */
6
7#include <common.h>
8#include <clk-uclass.h>
9#include <dm.h>
10#include <dm/device_compat.h>
11#include <asm/gpio.h>
12#include <dm/lists.h>
13#include <dm/device-internal.h>
14#include <regmap.h>
15#include <reset-uclass.h>
16#include <dt-bindings/phy/phy.h>
17
18#include <dt-bindings/phy/phy-ti.h>
19
20#define WIZ_MAX_INPUT_CLOCKS 4
21/* To include mux clocks, divider clocks and gate clocks */
22#define WIZ_MAX_OUTPUT_CLOCKS 32
23
24#define WIZ_MAX_LANES 4
25#define WIZ_MUX_NUM_CLOCKS 3
26#define WIZ_DIV_NUM_CLOCKS_16G 2
27#define WIZ_DIV_NUM_CLOCKS_10G 1
28
29#define WIZ_SERDES_CTRL 0x404
30#define WIZ_SERDES_TOP_CTRL 0x408
31#define WIZ_SERDES_RST 0x40c
32#define WIZ_SERDES_TYPEC 0x410
33#define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
34#define WIZ_LANEDIV(n) (0x484 + (0x40 * (n)))
35
36#define WIZ_MAX_LANES 4
37#define WIZ_MUX_NUM_CLOCKS 3
38#define WIZ_DIV_NUM_CLOCKS_16G 2
39#define WIZ_DIV_NUM_CLOCKS_10G 1
40
41#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
Sinthu Rajadae83a42023-03-13 18:12:24 +053042#define WIZ_SERDES_TYPEC_LN23_SWAP BIT(31)
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +053043
44enum wiz_lane_standard_mode {
45 LANE_MODE_GEN1,
46 LANE_MODE_GEN2,
47 LANE_MODE_GEN3,
48 LANE_MODE_GEN4,
49};
50
51enum wiz_refclk_mux_sel {
52 PLL0_REFCLK,
53 PLL1_REFCLK,
54 REFCLK_DIG,
55};
56
57enum wiz_refclk_div_sel {
58 CMN_REFCLK,
59 CMN_REFCLK1,
60};
61
62enum wiz_clock_input {
63 WIZ_CORE_REFCLK,
64 WIZ_EXT_REFCLK,
65 WIZ_CORE_REFCLK1,
66 WIZ_EXT_REFCLK1,
67};
68
Sinthu Rajadae83a42023-03-13 18:12:24 +053069/*
70 * List of master lanes used for lane swapping
71 */
72enum wiz_typec_master_lane {
73 LANE0 = 0,
74 LANE2 = 2,
75};
76
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +053077static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
78static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
79static const struct reg_field pll1_refclk_mux_sel =
80 REG_FIELD(WIZ_SERDES_RST, 29, 29);
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -070081static const struct reg_field pll1_refclk_mux_sel_2 =
82 REG_FIELD(WIZ_SERDES_RST, 22, 23);
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +053083static const struct reg_field pll0_refclk_mux_sel =
84 REG_FIELD(WIZ_SERDES_RST, 28, 28);
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -070085static const struct reg_field pll0_refclk_mux_sel_2 =
86 REG_FIELD(WIZ_SERDES_RST, 28, 29);
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +053087static const struct reg_field refclk_dig_sel_16g =
88 REG_FIELD(WIZ_SERDES_RST, 24, 25);
89static const struct reg_field refclk_dig_sel_10g =
90 REG_FIELD(WIZ_SERDES_RST, 24, 24);
91static const struct reg_field pma_cmn_refclk_int_mode =
92 REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -070093static const struct reg_field pma_cmn_refclk1_int_mode =
94 REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +053095static const struct reg_field pma_cmn_refclk_mode =
96 REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
97static const struct reg_field pma_cmn_refclk_dig_div =
98 REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
99static const struct reg_field pma_cmn_refclk1_dig_div =
100 REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
101
102static const struct reg_field p_enable[WIZ_MAX_LANES] = {
103 REG_FIELD(WIZ_LANECTL(0), 30, 31),
104 REG_FIELD(WIZ_LANECTL(1), 30, 31),
105 REG_FIELD(WIZ_LANECTL(2), 30, 31),
106 REG_FIELD(WIZ_LANECTL(3), 30, 31),
107};
108
109enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
110
111static const struct reg_field p_align[WIZ_MAX_LANES] = {
112 REG_FIELD(WIZ_LANECTL(0), 29, 29),
113 REG_FIELD(WIZ_LANECTL(1), 29, 29),
114 REG_FIELD(WIZ_LANECTL(2), 29, 29),
115 REG_FIELD(WIZ_LANECTL(3), 29, 29),
116};
117
118static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
119 REG_FIELD(WIZ_LANECTL(0), 28, 28),
120 REG_FIELD(WIZ_LANECTL(1), 28, 28),
121 REG_FIELD(WIZ_LANECTL(2), 28, 28),
122 REG_FIELD(WIZ_LANECTL(3), 28, 28),
123};
124
125static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
126 REG_FIELD(WIZ_LANECTL(0), 24, 25),
127 REG_FIELD(WIZ_LANECTL(1), 24, 25),
128 REG_FIELD(WIZ_LANECTL(2), 24, 25),
129 REG_FIELD(WIZ_LANECTL(3), 24, 25),
130};
131
132static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
133 REG_FIELD(WIZ_LANECTL(0), 22, 23),
134 REG_FIELD(WIZ_LANECTL(1), 22, 23),
135 REG_FIELD(WIZ_LANECTL(2), 22, 23),
136 REG_FIELD(WIZ_LANECTL(3), 22, 23),
137};
138
139static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
140 REG_FIELD(WIZ_LANEDIV(0), 16, 22),
141 REG_FIELD(WIZ_LANEDIV(1), 16, 22),
142 REG_FIELD(WIZ_LANEDIV(2), 16, 22),
143 REG_FIELD(WIZ_LANEDIV(3), 16, 22),
144};
145
146static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
147 REG_FIELD(WIZ_LANEDIV(0), 0, 8),
148 REG_FIELD(WIZ_LANEDIV(1), 0, 8),
149 REG_FIELD(WIZ_LANEDIV(2), 0, 8),
150 REG_FIELD(WIZ_LANEDIV(3), 0, 8),
151};
152
153struct wiz_clk_mux_sel {
154 enum wiz_refclk_mux_sel mux_sel;
155 u32 table[WIZ_MAX_INPUT_CLOCKS];
156 const char *node_name;
157 u32 num_parents;
158 u32 parents[WIZ_MAX_INPUT_CLOCKS];
159};
160
161struct wiz_clk_div_sel {
162 enum wiz_refclk_div_sel div_sel;
163 const char *node_name;
164};
165
166static struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
167 {
168 /*
169 * Mux value to be configured for each of the input clocks
170 * in the order populated in device tree
171 */
172 .num_parents = 2,
173 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
174 .mux_sel = PLL0_REFCLK,
175 .table = { 1, 0 },
176 .node_name = "pll0-refclk",
177 },
178 {
179 .num_parents = 2,
180 .parents = { WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK1 },
181 .mux_sel = PLL1_REFCLK,
182 .table = { 1, 0 },
183 .node_name = "pll1-refclk",
184 },
185 {
186 .num_parents = 4,
187 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK, WIZ_EXT_REFCLK1 },
188 .mux_sel = REFCLK_DIG,
189 .table = { 1, 3, 0, 2 },
190 .node_name = "refclk-dig",
191 },
192};
193
194static struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
195 {
196 /*
197 * Mux value to be configured for each of the input clocks
198 * in the order populated in device tree
199 */
200 .num_parents = 2,
201 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
202 .mux_sel = PLL0_REFCLK,
203 .table = { 1, 0 },
204 .node_name = "pll0-refclk",
205 },
206 {
207 .num_parents = 2,
208 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
209 .mux_sel = PLL1_REFCLK,
210 .table = { 1, 0 },
211 .node_name = "pll1-refclk",
212 },
213 {
214 .num_parents = 2,
215 .parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
216 .mux_sel = REFCLK_DIG,
217 .table = { 1, 0 },
218 .node_name = "refclk-dig",
219 },
220};
221
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -0700222static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
223 {
224 .num_parents = 3,
225 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
226 .table = { 2, 3, 0 },
227 .node_name = "pll0-refclk",
228 },
229 {
230 .num_parents = 3,
231 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
232 .table = { 2, 3, 0 },
233 .node_name = "pll1-refclk",
234 },
235 {
236 .num_parents = 3,
237 .parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
238 .table = { 2, 3, 0 },
239 .node_name = "refclk-dig",
240 },
241};
242
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530243static struct wiz_clk_div_sel clk_div_sel[] = {
244 {
245 .div_sel = CMN_REFCLK,
246 .node_name = "cmn-refclk-dig-div",
247 },
248 {
249 .div_sel = CMN_REFCLK1,
250 .node_name = "cmn-refclk1-dig-div",
251 },
252};
253
254enum wiz_type {
255 J721E_WIZ_16G,
256 J721E_WIZ_10G,
257 AM64_WIZ_10G,
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -0700258 J784S4_WIZ_10G,
Ravi Gunasekaran6a096e62023-05-15 16:20:40 +0530259 J721S2_WIZ_10G,
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530260};
261
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700262struct wiz_data {
263 enum wiz_type type;
264 const struct reg_field *pll0_refclk_mux_sel;
265 const struct reg_field *pll1_refclk_mux_sel;
266 const struct reg_field *refclk_dig_sel;
267 const struct reg_field *pma_cmn_refclk1_dig_div;
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -0700268 const struct reg_field *pma_cmn_refclk1_int_mode;
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700269 const struct wiz_clk_mux_sel *clk_mux_sel;
270 unsigned int clk_div_sel_num;
271};
272
273static const struct wiz_data j721e_16g_data = {
274 .type = J721E_WIZ_16G,
275 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
276 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
277 .refclk_dig_sel = &refclk_dig_sel_16g,
278 .pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
279 .clk_mux_sel = clk_mux_sel_16g,
280 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
281};
282
283static const struct wiz_data j721e_10g_data = {
284 .type = J721E_WIZ_10G,
285 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
286 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
287 .refclk_dig_sel = &refclk_dig_sel_10g,
288 .clk_mux_sel = clk_mux_sel_10g,
289 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
290};
291
292static struct wiz_data am64_10g_data = {
293 .type = AM64_WIZ_10G,
294 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
295 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
296 .refclk_dig_sel = &refclk_dig_sel_10g,
297 .clk_mux_sel = clk_mux_sel_10g,
298 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
299};
300
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -0700301static struct wiz_data j784s4_wiz_10g = {
302 .type = J784S4_WIZ_10G,
303 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2,
304 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2,
305 .refclk_dig_sel = &refclk_dig_sel_16g,
306 .pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode,
307 .clk_mux_sel = clk_mux_sel_10g_2_refclk,
308 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
309};
310
Ravi Gunasekaran6a096e62023-05-15 16:20:40 +0530311static struct wiz_data j721s2_10g_data = {
312 .type = J721S2_WIZ_10G,
313 .pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
314 .pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
315 .refclk_dig_sel = &refclk_dig_sel_10g,
316 .clk_mux_sel = clk_mux_sel_10g,
317 .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
318};
319
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530320#define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */
321#define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000
322
323struct wiz {
324 struct regmap *regmap;
325 enum wiz_type type;
326 struct wiz_clk_mux_sel *clk_mux_sel;
327 struct wiz_clk_div_sel *clk_div_sel;
328 unsigned int clk_div_sel_num;
329 struct regmap_field *por_en;
330 struct regmap_field *phy_reset_n;
331 struct regmap_field *phy_en_refclk;
332 struct regmap_field *p_enable[WIZ_MAX_LANES];
333 struct regmap_field *p_align[WIZ_MAX_LANES];
334 struct regmap_field *p_raw_auto_start[WIZ_MAX_LANES];
335 struct regmap_field *p_standard_mode[WIZ_MAX_LANES];
336 struct regmap_field *p_mac_div_sel0[WIZ_MAX_LANES];
337 struct regmap_field *p_mac_div_sel1[WIZ_MAX_LANES];
338 struct regmap_field *p0_fullrt_div[WIZ_MAX_LANES];
339 struct regmap_field *pma_cmn_refclk_int_mode;
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -0700340 struct regmap_field *pma_cmn_refclk1_int_mode;
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530341 struct regmap_field *pma_cmn_refclk_mode;
342 struct regmap_field *pma_cmn_refclk_dig_div;
343 struct regmap_field *pma_cmn_refclk1_dig_div;
344 struct regmap_field *div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
345 struct regmap_field *mux_sel_field[WIZ_MUX_NUM_CLOCKS];
346
347 struct udevice *dev;
348 u32 num_lanes;
349 struct gpio_desc *gpio_typec_dir;
350 u32 lane_phy_type[WIZ_MAX_LANES];
Sinthu Rajac5df75f2023-03-13 18:12:23 +0530351 u32 master_lane_num[WIZ_MAX_LANES];
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530352 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS];
353 unsigned int id;
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700354 const struct wiz_data *data;
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530355};
356
357struct wiz_div_clk {
358 struct clk parent_clk;
359 struct wiz *wiz;
360};
361
362struct wiz_mux_clk {
363 struct clk parent_clks[4];
364 struct wiz *wiz;
365};
366
367struct wiz_clk {
368 struct wiz *wiz;
369};
370
371struct wiz_reset {
372 struct wiz *wiz;
373};
374
375static ulong wiz_div_clk_get_rate(struct clk *clk)
376{
377 struct udevice *dev = clk->dev;
378 struct wiz_div_clk *priv = dev_get_priv(dev);
379 struct wiz_clk_div_sel *data = dev_get_plat(dev);
380 struct wiz *wiz = priv->wiz;
381 ulong parent_rate = clk_get_rate(&priv->parent_clk);
382 u32 val;
383
384 regmap_field_read(wiz->div_sel_field[data->div_sel], &val);
385
386 return parent_rate >> val;
387}
388
389static ulong wiz_div_clk_set_rate(struct clk *clk, ulong rate)
390{
391 struct udevice *dev = clk->dev;
392 struct wiz_div_clk *priv = dev_get_priv(dev);
393 struct wiz_clk_div_sel *data = dev_get_plat(dev);
394 struct wiz *wiz = priv->wiz;
395 ulong parent_rate = clk_get_rate(&priv->parent_clk);
396 u32 div = parent_rate / rate;
397
398 div = __ffs(div);
399 regmap_field_write(wiz->div_sel_field[data->div_sel], div);
400
401 return parent_rate >> div;
402}
403
404const struct clk_ops wiz_div_clk_ops = {
405 .get_rate = wiz_div_clk_get_rate,
406 .set_rate = wiz_div_clk_set_rate,
407};
408
409int wiz_div_clk_probe(struct udevice *dev)
410{
411 struct wiz_div_clk *priv = dev_get_priv(dev);
412 struct clk parent_clk;
413 int rc;
414
415 rc = clk_get_by_index(dev, 0, &parent_clk);
416 if (rc) {
417 dev_err(dev, "unable to get parent clock. ret %d\n", rc);
418 return rc;
419 }
420 priv->parent_clk = parent_clk;
421 priv->wiz = dev_get_priv(dev->parent);
422 return 0;
423}
424
425U_BOOT_DRIVER(wiz_div_clk) = {
426 .name = "wiz_div_clk",
427 .id = UCLASS_CLK,
428 .priv_auto = sizeof(struct wiz_div_clk),
429 .ops = &wiz_div_clk_ops,
430 .probe = wiz_div_clk_probe,
431};
432
433static int wiz_clk_mux_set_parent(struct clk *clk, struct clk *parent)
434{
435 struct udevice *dev = clk->dev;
436 struct wiz_mux_clk *priv = dev_get_priv(dev);
437 struct wiz_clk_mux_sel *data = dev_get_plat(dev);
438 struct wiz *wiz = priv->wiz;
439 int i;
440
441 for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++)
442 if (parent->dev == priv->parent_clks[i].dev)
443 break;
444
445 if (i == ARRAY_SIZE(priv->parent_clks))
446 return -EINVAL;
447
448 regmap_field_write(wiz->mux_sel_field[data->mux_sel], data->table[i]);
449 return 0;
450}
451
452static int wiz_clk_xlate(struct clk *clk, struct ofnode_phandle_args *args)
453{
454 struct udevice *dev = clk->dev;
455 struct wiz_mux_clk *priv = dev_get_priv(dev);
456 struct wiz *wiz = priv->wiz;
457
458 clk->id = wiz->id;
459
460 return 0;
461}
462
463static const struct clk_ops wiz_clk_mux_ops = {
464 .set_parent = wiz_clk_mux_set_parent,
465 .of_xlate = wiz_clk_xlate,
466};
467
468int wiz_mux_clk_probe(struct udevice *dev)
469{
470 struct wiz_mux_clk *priv = dev_get_priv(dev);
471 int rc;
472 int i;
473
474 for (i = 0; i < ARRAY_SIZE(priv->parent_clks); i++) {
475 rc = clk_get_by_index(dev, i, &priv->parent_clks[i]);
476 if (rc)
477 priv->parent_clks[i].dev = NULL;
478 }
479 priv->wiz = dev_get_priv(dev->parent);
480 return 0;
481}
482
483U_BOOT_DRIVER(wiz_mux_clk) = {
484 .name = "wiz_mux_clk",
485 .id = UCLASS_CLK,
486 .priv_auto = sizeof(struct wiz_mux_clk),
487 .ops = &wiz_clk_mux_ops,
488 .probe = wiz_mux_clk_probe,
489};
490
491static int wiz_clk_set_parent(struct clk *clk, struct clk *parent)
492{
493 struct udevice *dev = clk->dev;
494 struct wiz_clk *priv = dev_get_priv(dev);
495 const struct wiz_clk_mux_sel *mux_sel;
496 struct wiz *wiz = priv->wiz;
497 int num_parents;
498 int i, j, id;
499
500 id = clk->id >> 10;
501
502 /* set_parent is applicable only for MUX clocks */
503 if (id > TI_WIZ_REFCLK_DIG)
504 return 0;
505
506 for (i = 0; i < WIZ_MAX_INPUT_CLOCKS; i++)
507 if (wiz->input_clks[i]->dev == parent->dev)
508 break;
509
510 if (i == WIZ_MAX_INPUT_CLOCKS)
511 return -EINVAL;
512
513 mux_sel = &wiz->clk_mux_sel[id];
514 num_parents = mux_sel->num_parents;
515 for (j = 0; j < num_parents; j++)
516 if (mux_sel->parents[j] == i)
517 break;
518
519 if (j == num_parents)
520 return -EINVAL;
521
522 regmap_field_write(wiz->mux_sel_field[id], mux_sel->table[j]);
523
524 return 0;
525}
526
527static int wiz_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
528{
529 struct udevice *dev = clk->dev;
530 struct wiz_clk *priv = dev_get_priv(dev);
531 struct wiz *wiz = priv->wiz;
532
533 clk->id = args->args[0] << 10 | wiz->id;
534
535 return 0;
536}
537
538static const struct clk_ops wiz_clk_ops = {
539 .set_parent = wiz_clk_set_parent,
540 .of_xlate = wiz_clk_of_xlate,
541};
542
543int wiz_clk_probe(struct udevice *dev)
544{
545 struct wiz_clk *priv = dev_get_priv(dev);
546
547 priv->wiz = dev_get_priv(dev->parent);
548
549 return 0;
550}
551
552U_BOOT_DRIVER(wiz_clk) = {
553 .name = "wiz_clk",
554 .id = UCLASS_CLK,
555 .priv_auto = sizeof(struct wiz_clk),
556 .ops = &wiz_clk_ops,
557 .probe = wiz_clk_probe,
558};
559
560static int wiz_reset_request(struct reset_ctl *reset_ctl)
561{
562 return 0;
563}
564
565static int wiz_reset_free(struct reset_ctl *reset_ctl)
566{
567 return 0;
568}
569
570static int wiz_reset_assert(struct reset_ctl *reset_ctl)
571{
572 struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
573 struct wiz *wiz = priv->wiz;
574 int ret;
575 int id = reset_ctl->id;
576
577 if (id == 0) {
578 ret = regmap_field_write(wiz->phy_reset_n, false);
579 return ret;
580 }
581
582 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
583 return ret;
584}
585
586static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
587{
588 if (wiz->type != AM64_WIZ_10G)
589 return 0;
590
591 if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
592 return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
593
594 return 0;
595}
596
597static int wiz_reset_deassert(struct reset_ctl *reset_ctl)
598{
599 struct wiz_reset *priv = dev_get_priv(reset_ctl->dev);
600 struct wiz *wiz = priv->wiz;
601 int ret;
602 int id = reset_ctl->id;
603
604 ret = wiz_phy_fullrt_div(wiz, id - 1);
605 if (ret)
606 return ret;
607
608 /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
Sinthu Rajac5df75f2023-03-13 18:12:23 +0530609 if (id == 0) {
610 if (wiz->gpio_typec_dir) {
611 if (dm_gpio_get_value(wiz->gpio_typec_dir)) {
612 regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
613 WIZ_SERDES_TYPEC_LN10_SWAP,
614 WIZ_SERDES_TYPEC_LN10_SWAP);
615 } else {
616 regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
617 WIZ_SERDES_TYPEC_LN10_SWAP, 0);
618 }
619 }
620 } else {
621 /* if no typec-dir gpio was specified and PHY type is
622 * USB3 with master lane number is '0', set LN10 SWAP
623 * bit to '1'
624 */
625 u32 num_lanes = wiz->num_lanes;
626 int i;
627
628 for (i = 0; i < num_lanes; i++) {
Sinthu Rajadae83a42023-03-13 18:12:24 +0530629 if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
630 switch (wiz->master_lane_num[i]) {
631 case LANE0:
Sinthu Rajac5df75f2023-03-13 18:12:23 +0530632 regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
633 WIZ_SERDES_TYPEC_LN10_SWAP,
634 WIZ_SERDES_TYPEC_LN10_SWAP);
Sinthu Rajadae83a42023-03-13 18:12:24 +0530635 break;
636 case LANE2:
637 regmap_update_bits(wiz->regmap, WIZ_SERDES_TYPEC,
638 WIZ_SERDES_TYPEC_LN23_SWAP,
639 WIZ_SERDES_TYPEC_LN23_SWAP);
640 break;
641 default:
642 break;
643 }
644 }
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530645 }
646 }
647
648 if (id == 0) {
649 ret = regmap_field_write(wiz->phy_reset_n, true);
650 return ret;
651 }
652
Aswath Govindrajueaf8b512022-01-28 13:41:37 +0530653 if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530654 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
655 else
656 ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
657
658 return ret;
659}
660
661static struct reset_ops wiz_reset_ops = {
662 .request = wiz_reset_request,
663 .rfree = wiz_reset_free,
664 .rst_assert = wiz_reset_assert,
665 .rst_deassert = wiz_reset_deassert,
666};
667
668int wiz_reset_probe(struct udevice *dev)
669{
670 struct wiz_reset *priv = dev_get_priv(dev);
671
672 priv->wiz = dev_get_priv(dev->parent);
673
674 return 0;
675}
676
677U_BOOT_DRIVER(wiz_reset) = {
678 .name = "wiz-reset",
679 .id = UCLASS_RESET,
680 .probe = wiz_reset_probe,
681 .ops = &wiz_reset_ops,
682 .flags = DM_FLAG_LEAVE_PD_ON,
683};
684
685static int wiz_reset(struct wiz *wiz)
686{
687 int ret;
688
689 ret = regmap_field_write(wiz->por_en, 0x1);
690 if (ret)
691 return ret;
692
693 mdelay(1);
694
695 ret = regmap_field_write(wiz->por_en, 0x0);
696 if (ret)
697 return ret;
698
699 return 0;
700}
701
702static int wiz_p_mac_div_sel(struct wiz *wiz)
703{
704 u32 num_lanes = wiz->num_lanes;
705 int ret;
706 int i;
707
708 for (i = 0; i < num_lanes; i++) {
709 if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
710 ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
711 if (ret)
712 return ret;
713
714 ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
715 if (ret)
716 return ret;
717 }
718 }
719
720 return 0;
721}
722
723static int wiz_mode_select(struct wiz *wiz)
724{
725 u32 num_lanes = wiz->num_lanes;
726 int ret;
727 int i;
728
729 for (i = 0; i < num_lanes; i++) {
730 if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
731 ret = regmap_field_write(wiz->p_standard_mode[i],
732 LANE_MODE_GEN2);
733 if (ret)
734 return ret;
735 }
736 }
737
738 return 0;
739}
740
741static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
742{
743 u32 num_lanes = wiz->num_lanes;
744 int i;
745 int ret;
746
747 for (i = 0; i < num_lanes; i++) {
748 ret = regmap_field_write(wiz->p_align[i], enable);
749 if (ret)
750 return ret;
751
752 ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
753 if (ret)
754 return ret;
755 }
756
757 return 0;
758}
759
760static int wiz_init(struct wiz *wiz)
761{
762 struct udevice *dev = wiz->dev;
763 int ret;
764
765 ret = wiz_reset(wiz);
766 if (ret) {
767 dev_err(dev, "WIZ reset failed\n");
768 return ret;
769 }
770
771 ret = wiz_mode_select(wiz);
772 if (ret) {
773 dev_err(dev, "WIZ mode select failed\n");
774 return ret;
775 }
776
777 ret = wiz_p_mac_div_sel(wiz);
778 if (ret) {
779 dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
780 return ret;
781 }
782
783 ret = wiz_init_raw_interface(wiz, true);
784 if (ret) {
785 dev_err(dev, "WIZ interface initialization failed\n");
786 return ret;
787 }
788
789 return 0;
790}
791
792static int wiz_regfield_init(struct wiz *wiz)
793{
794 struct regmap *regmap = wiz->regmap;
795 int num_lanes = wiz->num_lanes;
796 struct udevice *dev = wiz->dev;
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700797 const struct wiz_data *data = wiz->data;
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530798 int i;
799
800 wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
801 if (IS_ERR(wiz->por_en)) {
802 dev_err(dev, "POR_EN reg field init failed\n");
803 return PTR_ERR(wiz->por_en);
804 }
805
806 wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
807 phy_reset_n);
808 if (IS_ERR(wiz->phy_reset_n)) {
809 dev_err(dev, "PHY_RESET_N reg field init failed\n");
810 return PTR_ERR(wiz->phy_reset_n);
811 }
812
813 wiz->pma_cmn_refclk_int_mode =
814 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
815 if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
816 dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
817 return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
818 }
819
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -0700820 if (data->pma_cmn_refclk1_int_mode) {
821 wiz->pma_cmn_refclk1_int_mode =
822 devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_int_mode);
823 if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
824 dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
825 return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
826 }
827 }
828
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530829 wiz->pma_cmn_refclk_mode =
830 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
831 if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
832 dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
833 return PTR_ERR(wiz->pma_cmn_refclk_mode);
834 }
835
836 wiz->div_sel_field[CMN_REFCLK] =
837 devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
838 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK])) {
839 dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
840 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]);
841 }
842
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700843 if (data->pma_cmn_refclk1_dig_div) {
844 wiz->div_sel_field[CMN_REFCLK1] =
845 devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_dig_div);
846 if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
847 dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
848 return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
849 }
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530850 }
851
852 wiz->mux_sel_field[PLL0_REFCLK] =
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700853 devm_regmap_field_alloc(dev, regmap, *data->pll0_refclk_mux_sel);
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530854 if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
855 dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
856 return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
857 }
858
859 wiz->mux_sel_field[PLL1_REFCLK] =
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700860 devm_regmap_field_alloc(dev, regmap, *data->pll1_refclk_mux_sel);
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530861 if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
862 dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
863 return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
864 }
865
Matt Ranostay6d255cc2022-07-07 23:41:52 -0700866 wiz->mux_sel_field[REFCLK_DIG] =
867 devm_regmap_field_alloc(dev, regmap, *data->refclk_dig_sel);
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530868 if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
869 dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
870 return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
871 }
872
873 for (i = 0; i < num_lanes; i++) {
874 wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
875 p_enable[i]);
876 if (IS_ERR(wiz->p_enable[i])) {
877 dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
878 return PTR_ERR(wiz->p_enable[i]);
879 }
880
881 wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
882 p_align[i]);
883 if (IS_ERR(wiz->p_align[i])) {
884 dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
885 return PTR_ERR(wiz->p_align[i]);
886 }
887
888 wiz->p_raw_auto_start[i] =
889 devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
890 if (IS_ERR(wiz->p_raw_auto_start[i])) {
891 dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
892 i);
893 return PTR_ERR(wiz->p_raw_auto_start[i]);
894 }
895
896 wiz->p_standard_mode[i] =
897 devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
898 if (IS_ERR(wiz->p_standard_mode[i])) {
899 dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
900 i);
901 return PTR_ERR(wiz->p_standard_mode[i]);
902 }
903
904 wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
905 if (IS_ERR(wiz->p0_fullrt_div[i])) {
906 dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
907 return PTR_ERR(wiz->p0_fullrt_div[i]);
908 }
909
910 wiz->p_mac_div_sel0[i] =
911 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
912 if (IS_ERR(wiz->p_mac_div_sel0[i])) {
913 dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
914 i);
915 return PTR_ERR(wiz->p_mac_div_sel0[i]);
916 }
917
918 wiz->p_mac_div_sel1[i] =
919 devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
920 if (IS_ERR(wiz->p_mac_div_sel1[i])) {
921 dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
922 i);
923 return PTR_ERR(wiz->p_mac_div_sel1[i]);
924 }
925 }
926
927 return 0;
928}
929
930static int wiz_clock_init(struct wiz *wiz)
931{
932 struct udevice *dev = wiz->dev;
933 unsigned long rate;
934 struct clk *clk;
935 int ret;
936
937 clk = devm_clk_get(dev, "core_ref_clk");
938 if (IS_ERR(clk)) {
939 dev_err(dev, "core_ref_clk clock not found\n");
940 ret = PTR_ERR(clk);
941 return ret;
942 }
943 wiz->input_clks[WIZ_CORE_REFCLK] = clk;
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530944
945 rate = clk_get_rate(clk);
946 if (rate >= 100000000)
947 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
948 else
949 regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
950
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -0700951 if (wiz->data->pma_cmn_refclk1_int_mode) {
952 clk = devm_clk_get(dev, "core_ref1_clk");
953 if (IS_ERR(clk)) {
954 dev_err(dev, "core_ref1_clk clock not found\n");
955 ret = PTR_ERR(clk);
956 return ret;
957 }
958 wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
959
960 rate = clk_get_rate(clk);
961 if (rate >= 100000000)
962 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
963 else
964 regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
965 } else {
966 /* Initialize CORE_REFCLK1 to the same clock reference to maintain old DT compatibility */
967 wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
968 }
969
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +0530970 clk = devm_clk_get(dev, "ext_ref_clk");
971 if (IS_ERR(clk)) {
972 dev_err(dev, "ext_ref_clk clock not found\n");
973 ret = PTR_ERR(clk);
974 return ret;
975 }
976
977 wiz->input_clks[WIZ_EXT_REFCLK] = clk;
978 /* Initialize EXT_REFCLK1 to the same clock reference to maintain old DT compatibility */
979 wiz->input_clks[WIZ_EXT_REFCLK1] = clk;
980
981 rate = clk_get_rate(clk);
982 if (rate >= 100000000)
983 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
984 else
985 regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
986
987 return 0;
988}
989
990static ofnode get_child_by_name(struct udevice *dev, const char *name)
991{
992 int l = strlen(name);
993 ofnode node = dev_read_first_subnode(dev);
994
995 while (ofnode_valid(node)) {
996 const char *child_name = ofnode_get_name(node);
997
998 if (!strncmp(child_name, name, l)) {
999 if (child_name[l] == '\0' || child_name[l] == '@')
1000 return node;
1001 }
1002 node = dev_read_next_subnode(node);
1003 }
1004 return node;
1005}
1006
1007static int j721e_wiz_bind_clocks(struct wiz *wiz)
1008{
1009 struct udevice *dev = wiz->dev;
1010 struct driver *wiz_clk_drv;
1011 int i, rc;
1012
1013 wiz_clk_drv = lists_driver_lookup_name("wiz_clk");
1014 if (!wiz_clk_drv) {
1015 dev_err(dev, "Cannot find driver 'wiz_clk'\n");
1016 return -ENOENT;
1017 }
1018
1019 for (i = 0; i < WIZ_DIV_NUM_CLOCKS_10G; i++) {
1020 rc = device_bind(dev, wiz_clk_drv, clk_div_sel[i].node_name,
1021 &clk_div_sel[i], dev_ofnode(dev), NULL);
1022 if (rc) {
1023 dev_err(dev, "cannot bind driver for clock %s\n",
1024 clk_div_sel[i].node_name);
1025 }
1026 }
1027
1028 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1029 rc = device_bind(dev, wiz_clk_drv, clk_mux_sel_10g[i].node_name,
1030 &clk_mux_sel_10g[i], dev_ofnode(dev), NULL);
1031 if (rc) {
1032 dev_err(dev, "cannot bind driver for clock %s\n",
1033 clk_mux_sel_10g[i].node_name);
1034 }
1035 }
1036
1037 return 0;
1038}
1039
1040static int j721e_wiz_bind_of_clocks(struct wiz *wiz)
1041{
1042 struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1043 struct udevice *dev = wiz->dev;
1044 enum wiz_type type = wiz->type;
1045 struct driver *div_clk_drv;
1046 struct driver *mux_clk_drv;
1047 ofnode node;
1048 int i, rc;
1049
Ravi Gunasekaran6a096e62023-05-15 16:20:40 +05301050 switch (type) {
1051 case AM64_WIZ_10G:
1052 case J784S4_WIZ_10G:
1053 case J721S2_WIZ_10G:
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301054 return j721e_wiz_bind_clocks(wiz);
Ravi Gunasekaran6a096e62023-05-15 16:20:40 +05301055 default:
1056 break;
1057 };
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301058
1059 div_clk_drv = lists_driver_lookup_name("wiz_div_clk");
1060 if (!div_clk_drv) {
1061 dev_err(dev, "Cannot find driver 'wiz_div_clk'\n");
1062 return -ENOENT;
1063 }
1064
1065 mux_clk_drv = lists_driver_lookup_name("wiz_mux_clk");
1066 if (!mux_clk_drv) {
1067 dev_err(dev, "Cannot find driver 'wiz_mux_clk'\n");
1068 return -ENOENT;
1069 }
1070
1071 for (i = 0; i < wiz->clk_div_sel_num; i++) {
1072 node = get_child_by_name(dev, clk_div_sel[i].node_name);
1073 if (!ofnode_valid(node)) {
1074 dev_err(dev, "cannot find node for clock %s\n",
1075 clk_div_sel[i].node_name);
1076 continue;
1077 }
1078 rc = device_bind(dev, div_clk_drv, clk_div_sel[i].node_name,
1079 &clk_div_sel[i], node, NULL);
1080 if (rc) {
1081 dev_err(dev, "cannot bind driver for clock %s\n",
1082 clk_div_sel[i].node_name);
1083 }
1084 }
1085
1086 for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1087 node = get_child_by_name(dev, clk_mux_sel[i].node_name);
1088 if (!ofnode_valid(node)) {
1089 dev_err(dev, "cannot find node for clock %s\n",
1090 clk_mux_sel[i].node_name);
1091 continue;
1092 }
1093 rc = device_bind(dev, mux_clk_drv, clk_mux_sel[i].node_name,
1094 &clk_mux_sel[i], node, NULL);
1095 if (rc) {
1096 dev_err(dev, "cannot bind driver for clock %s\n",
1097 clk_mux_sel[i].node_name);
1098 }
1099 }
1100
1101 return 0;
1102}
1103
1104static int j721e_wiz_bind_reset(struct udevice *dev)
1105{
1106 int rc;
1107 struct driver *drv;
1108
1109 drv = lists_driver_lookup_name("wiz-reset");
1110 if (!drv) {
1111 dev_err(dev, "Cannot find driver 'wiz-reset'\n");
1112 return -ENOENT;
1113 }
1114
1115 rc = device_bind(dev, drv, "wiz-reset", NULL, dev_ofnode(dev), NULL);
1116 if (rc) {
1117 dev_err(dev, "cannot bind driver for wiz-reset\n");
1118 return rc;
1119 }
1120
1121 return 0;
1122}
1123
1124static int j721e_wiz_bind(struct udevice *dev)
1125{
1126 dm_scan_fdt_dev(dev);
1127
1128 return 0;
1129}
1130
1131static int wiz_get_lane_phy_types(struct udevice *dev, struct wiz *wiz)
1132{
1133 ofnode child, serdes;
1134
1135 serdes = get_child_by_name(dev, "serdes");
1136 if (!ofnode_valid(serdes)) {
1137 dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1138 return -EINVAL;
1139 }
1140
1141 ofnode_for_each_subnode(child, serdes) {
1142 u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1143 int ret, i;
1144
1145 ret = ofnode_read_u32(child, "reg", &reg);
1146 if (ret) {
1147 dev_err(dev, "%s: Reading \"reg\" from failed: %d\n",
1148 __func__, ret);
1149 return ret;
1150 }
1151 ofnode_read_u32(child, "cdns,num-lanes", &num_lanes);
1152 ofnode_read_u32(child, "cdns,phy-type", &phy_type);
1153
1154 dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1155 reg, reg + num_lanes - 1, phy_type);
1156
Sinthu Rajac5df75f2023-03-13 18:12:23 +05301157 for (i = reg; i < reg + num_lanes; i++) {
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301158 wiz->lane_phy_type[i] = phy_type;
Sinthu Rajac5df75f2023-03-13 18:12:23 +05301159 wiz->master_lane_num[i] = reg;
1160 }
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301161 }
1162
1163 return 0;
1164}
1165
1166static int j721e_wiz_probe(struct udevice *dev)
1167{
1168 struct wiz *wiz = dev_get_priv(dev);
1169 struct ofnode_phandle_args args;
1170 unsigned int val;
1171 int rc, i;
1172 ofnode node;
1173 struct regmap *regmap;
1174 u32 num_lanes;
1175
1176 node = get_child_by_name(dev, "serdes");
1177
1178 if (!ofnode_valid(node)) {
1179 dev_err(dev, "Failed to get SERDES child DT node\n");
1180 return -ENODEV;
1181 }
1182
1183 rc = regmap_init_mem(node, &regmap);
1184 if (rc) {
1185 dev_err(dev, "Failed to get memory resource\n");
1186 return rc;
1187 }
1188 rc = dev_read_u32(dev, "num-lanes", &num_lanes);
1189 if (rc) {
1190 dev_err(dev, "Failed to read num-lanes property\n");
1191 goto err_addr_to_resource;
1192 }
1193
1194 if (num_lanes > WIZ_MAX_LANES) {
1195 dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1196 goto err_addr_to_resource;
1197 }
1198
1199 wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1200 GPIOD_IS_IN);
1201 if (IS_ERR(wiz->gpio_typec_dir)) {
1202 rc = PTR_ERR(wiz->gpio_typec_dir);
1203 dev_err(dev, "Failed to request typec-dir gpio: %d\n", rc);
1204 goto err_addr_to_resource;
1205 }
1206
1207 rc = dev_read_phandle_with_args(dev, "power-domains", "#power-domain-cells", 0, 0, &args);
1208 if (rc) {
1209 dev_err(dev, "Failed to get power domain: %d\n", rc);
1210 goto err_addr_to_resource;
1211 }
1212
1213 wiz->id = args.args[0];
1214 wiz->regmap = regmap;
1215 wiz->num_lanes = num_lanes;
1216 wiz->dev = dev;
1217 wiz->clk_div_sel = clk_div_sel;
Matt Ranostay6d255cc2022-07-07 23:41:52 -07001218
1219 wiz->data = (struct wiz_data *)dev_get_driver_data(dev);
1220 wiz->type = wiz->data->type;
1221
1222 wiz->clk_mux_sel = (struct wiz_clk_mux_sel *)wiz->data->clk_mux_sel;
1223 wiz->clk_div_sel_num = wiz->data->clk_div_sel_num;
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301224
1225 rc = wiz_get_lane_phy_types(dev, wiz);
1226 if (rc) {
1227 dev_err(dev, "Failed to get lane PHY types\n");
1228 goto err_addr_to_resource;
1229 }
1230
1231 rc = wiz_regfield_init(wiz);
1232 if (rc) {
1233 dev_err(dev, "Failed to initialize regfields\n");
1234 goto err_addr_to_resource;
1235 }
1236
1237 for (i = 0; i < wiz->num_lanes; i++) {
1238 regmap_field_read(wiz->p_enable[i], &val);
1239 if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1240 dev_err(dev, "SERDES already configured\n");
1241 rc = -EBUSY;
1242 goto err_addr_to_resource;
1243 }
1244 }
1245
1246 rc = j721e_wiz_bind_of_clocks(wiz);
1247 if (rc) {
1248 dev_err(dev, "Failed to bind clocks\n");
1249 goto err_addr_to_resource;
1250 }
1251
1252 rc = j721e_wiz_bind_reset(dev);
1253 if (rc) {
1254 dev_err(dev, "Failed to bind reset\n");
1255 goto err_addr_to_resource;
1256 }
1257
1258 rc = wiz_clock_init(wiz);
1259 if (rc) {
1260 dev_warn(dev, "Failed to initialize clocks\n");
1261 goto err_addr_to_resource;
1262 }
1263
1264 rc = wiz_init(wiz);
1265 if (rc) {
1266 dev_err(dev, "WIZ initialization failed\n");
1267 goto err_addr_to_resource;
1268 }
1269
1270 return 0;
1271
1272err_addr_to_resource:
1273 free(regmap);
1274
1275 return rc;
1276}
1277
1278static int j721e_wiz_remove(struct udevice *dev)
1279{
1280 struct wiz *wiz = dev_get_priv(dev);
1281
1282 if (wiz->regmap)
1283 free(wiz->regmap);
1284
1285 return 0;
1286}
1287
1288static const struct udevice_id j721e_wiz_ids[] = {
1289 {
Matt Ranostay6d255cc2022-07-07 23:41:52 -07001290 .compatible = "ti,j721e-wiz-16g", .data = (ulong)&j721e_16g_data,
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301291 },
1292 {
Matt Ranostay6d255cc2022-07-07 23:41:52 -07001293 .compatible = "ti,j721e-wiz-10g", .data = (ulong)&j721e_10g_data,
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301294 },
1295 {
Matt Ranostay6d255cc2022-07-07 23:41:52 -07001296 .compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data,
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301297 },
Matt Ranostayb7c6fbb2022-10-05 13:51:30 -07001298 {
1299 .compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g,
1300 },
Ravi Gunasekaran6a096e62023-05-15 16:20:40 +05301301 {
1302 .compatible = "ti,j721s2-wiz-10g", .data = (ulong)&j721s2_10g_data,
1303 },
Jean-Jacques Hiblot065788e2021-07-21 21:28:38 +05301304 {}
1305};
1306
1307U_BOOT_DRIVER(phy_j721e_wiz) = {
1308 .name = "phy-j721e-wiz",
1309 .id = UCLASS_NOP,
1310 .of_match = j721e_wiz_ids,
1311 .bind = j721e_wiz_bind,
1312 .probe = j721e_wiz_probe,
1313 .remove = j721e_wiz_remove,
1314 .priv_auto = sizeof(struct wiz),
1315 .flags = DM_FLAG_LEAVE_PD_ON,
1316};