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git01.mediatek.com / filogic / uboot / 8b084379bd89d0b4bbf171304bbd8049ab49293c / . / include / configs / at91sam9rlek.h
blob: 0105cb0a80e24b0bfef1eed5981c7948e823a60d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]2/*
3 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +0100[diff] [blame]4 * Stelian Pop <stelian@popies.net>
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]5 * Lead Tech Design <www.leadtechdesign.com>
6 *
7 * Configuation settings for the AT91SAM9RLEK board.
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]8 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
Xu, Hong0c0fb212011-08-01 03:56:53 +0000[diff] [blame]13#include <asm/hardware.h>
14
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]15/* ARM asynchronous clock */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000[diff] [blame]16#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
17#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* main clock xtal */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]18
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]19/*
20 * Hardware drivers
21 */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000[diff] [blame]22
Stelian Popcea5c532008-05-08 14:52:32 +0200[diff] [blame]23/* LCD */
Stelian Popcea5c532008-05-08 14:52:32 +0200[diff] [blame]24#define LCD_BPP LCD_COLOR8
Xu, Hong0c0fb212011-08-01 03:56:53 +0000[diff] [blame]25/* Let board_init_f handle the framebuffer allocation */
26#undef CONFIG_FB_ADDR
Xu, Hong0c0fb212011-08-01 03:56:53 +0000[diff] [blame]27
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]28/* SDRAM */
Xu, Hong0c0fb212011-08-01 03:56:53 +0000[diff] [blame]29#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
30#define CONFIG_SYS_SDRAM_SIZE 0x04000000
31
32#define CONFIG_SYS_INIT_SP_ADDR \
Wenyou Yang3cbbeb12017-04-18 15:28:27 +0800[diff] [blame]33 (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]34
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]35/* NAND flash */
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]36#ifdef CONFIG_CMD_NAND
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]37#define CONFIG_SYS_MAX_NAND_DEVICE 1
Xu, Hong0c0fb212011-08-01 03:56:53 +0000[diff] [blame]38#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]39#define CONFIG_SYS_NAND_DBW_8 1
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]40/* our ALE is AD21 */
41#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
42/* our CLE is AD22 */
43#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
44#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PB6
45#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD17
Wolfgang Denk1f797742009-07-18 21:52:24 +0200[diff] [blame]46
Jean-Christophe PLAGNIOL-VILLARDc9539ba2009-03-22 10:22:34 +0100[diff] [blame]47#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]48
49/* Ethernet - not present */
50
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]51#ifdef CONFIG_SYS_USE_DATAFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]52
53/* bootstrap + u-boot + env + linux in dataflash on CS0 */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]54
Wu, Josh7ff194f2015-02-02 17:51:01 +0800[diff] [blame]55#elif CONFIG_SYS_USE_NANDFLASH
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]56
57/* bootstrap + u-boot + env + linux in nandflash */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]58
Wu, Josh7ff194f2015-02-02 17:51:01 +0800[diff] [blame]59#else /* CONFIG_SYS_USE_MMC */
60
61/* bootstrap + u-boot + env + linux in mmc */
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]62#endif
Stelian Pop0bf5cad2008-05-08 18:52:25 +0200[diff] [blame]63#endif