| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2016 Imagination Technologies |
| Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| Simon Glass | 6980b6b | 2019-11-14 12:57:45 -0700 | [diff] [blame] | 7 | #include <init.h> |
| Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 8 | |
| 9 | #include <asm/io.h> |
| 10 | |
| 11 | #include "boston-regs.h" |
| 12 | |
| Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 13 | DECLARE_GLOBAL_DATA_PTR; |
| 14 | |
| Simon Glass | d35f338 | 2017-04-06 12:47:05 -0600 | [diff] [blame] | 15 | int dram_init(void) |
| Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 16 | { |
| 17 | u32 ddrconf0 = __raw_readl((uint32_t *)BOSTON_PLAT_DDRCONF0); |
| 18 | |
| Simon Glass | 39f90ba | 2017-03-31 08:40:25 -0600 | [diff] [blame] | 19 | gd->ram_size = (phys_size_t)(ddrconf0 & BOSTON_PLAT_DDRCONF0_SIZE) << |
| 20 | 30; |
| 21 | |
| 22 | return 0; |
| Paul Burton | f5de32a | 2016-09-08 07:47:39 +0100 | [diff] [blame] | 23 | } |
| 24 | |
| 25 | ulong board_get_usable_ram_top(ulong total_size) |
| 26 | { |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
| 29 | if (gd->ram_top < CONFIG_SYS_SDRAM_BASE) { |
| 30 | /* 2GB wrapped around to 0 */ |
| 31 | return CKSEG0ADDR(256 << 20); |
| 32 | } |
| 33 | |
| 34 | return min_t(unsigned long, gd->ram_top, CKSEG0ADDR(256 << 20)); |
| 35 | } |