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Simon Glassb2c1cac2014-02-26 15:59:21 -07001/dts-v1/;
2
Patrick Delaunay23aee612020-01-13 11:35:13 +01003#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +01005#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -04006#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05307#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +01008
Simon Glassb2c1cac2014-02-26 15:59:21 -07009/ {
10 model = "sandbox";
11 compatible = "sandbox";
12 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060013 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070014
Simon Glassfef72b72014-07-23 06:55:03 -060015 aliases {
16 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010017 ethernet0 = "/eth@10002000";
18 ethernet2 = &swp_0;
19 ethernet3 = &eth_3;
20 ethernet4 = &dsa_eth0;
21 ethernet5 = &eth_5;
Simon Glass5620cf82018-10-01 12:22:40 -060022 gpio1 = &gpio_a;
23 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010024 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070025 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060026 mmc0 = "/mmc0";
27 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070028 pci0 = &pci0;
29 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070030 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020031 remoteproc0 = &rproc_1;
32 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060033 rtc0 = &rtc_0;
34 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060035 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020036 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070037 testbus3 = "/some-bus";
38 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070039 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070040 testfdt3 = "/b-test";
41 testfdt5 = "/some-bus/c-test@5";
42 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070043 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020044 fdt-dummy0 = "/translation-test@8000/dev@0,0";
45 fdt-dummy1 = "/translation-test@8000/dev@1,100";
46 fdt-dummy2 = "/translation-test@8000/dev@2,200";
47 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060048 usb0 = &usb_0;
49 usb1 = &usb_1;
50 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020051 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020052 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060053 };
54
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020055 config {
56 environment {
57 from_fdt = "yes";
58 fdt_env_path = "";
59 };
60 };
61
Simon Glassed96cde2018-12-10 10:37:33 -070062 audio: audio-codec {
63 compatible = "sandbox,audio-codec";
64 #sound-dai-cells = <1>;
65 };
66
Philippe Reynes1ee26482020-07-24 18:19:51 +020067 buttons {
68 compatible = "gpio-keys";
69
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020070 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020071 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020072 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +020073 };
74
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020075 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +020076 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +020077 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +020078 };
79 };
80
Marek Szyprowskiad398592021-02-18 11:33:18 +010081 buttons2 {
82 compatible = "adc-keys";
83 io-channels = <&adc 3>;
84 keyup-threshold-microvolt = <3000000>;
85
86 button-up {
87 label = "button3";
88 linux,code = <KEY_F3>;
89 press-threshold-microvolt = <1500000>;
90 };
91
92 button-down {
93 label = "button4";
94 linux,code = <KEY_F4>;
95 press-threshold-microvolt = <1000000>;
96 };
97
98 button-enter {
99 label = "button5";
100 linux,code = <KEY_F5>;
101 press-threshold-microvolt = <500000>;
102 };
103 };
104
Simon Glassc953aaf2018-12-10 10:37:34 -0700105 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600106 reg = <0 0>;
107 compatible = "google,cros-ec-sandbox";
108
109 /*
110 * This describes the flash memory within the EC. Note
111 * that the STM32L flash erases to 0, not 0xff.
112 */
113 flash {
114 image-pos = <0x08000000>;
115 size = <0x20000>;
116 erase-value = <0>;
117
118 /* Information for sandbox */
119 ro {
120 image-pos = <0>;
121 size = <0xf000>;
122 };
123 wp-ro {
124 image-pos = <0xf000>;
125 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700126 used = <0x884>;
127 compress = "lz4";
128 uncomp-size = <0xcf8>;
129 hash {
130 algo = "sha256";
131 value = [00 01 02 03 04 05 06 07
132 08 09 0a 0b 0c 0d 0e 0f
133 10 11 12 13 14 15 16 17
134 18 19 1a 1b 1c 1d 1e 1f];
135 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600136 };
137 rw {
138 image-pos = <0x10000>;
139 size = <0x10000>;
140 };
141 };
142 };
143
Yannick Fertré9712c822019-10-07 15:29:05 +0200144 dsi_host: dsi_host {
145 compatible = "sandbox,dsi-host";
146 };
147
Simon Glassb2c1cac2014-02-26 15:59:21 -0700148 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600149 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700150 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600151 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700152 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600153 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100154 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
155 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700156 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100157 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
158 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
159 <&gpio_b 7 GPIO_IN 3 2 1>,
160 <&gpio_b 8 GPIO_OUT 3 2 1>,
161 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100162 test3-gpios =
163 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
164 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
165 <&gpio_c 2 GPIO_OUT>,
166 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
167 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200168 <&gpio_c 5 GPIO_IN>,
169 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
170 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530171 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
172 test5-gpios = <&gpio_a 19>;
173
Simon Glass6df01f92018-12-10 10:37:37 -0700174 int-value = <1234>;
175 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200176 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200177 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600178 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700179 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600180 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200181 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530182
183 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
184 <&muxcontroller0 2>, <&muxcontroller0 3>,
185 <&muxcontroller1>;
186 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
187 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100188 display-timings {
189 timing0: 240x320 {
190 clock-frequency = <6500000>;
191 hactive = <240>;
192 vactive = <320>;
193 hfront-porch = <6>;
194 hback-porch = <7>;
195 hsync-len = <1>;
196 vback-porch = <5>;
197 vfront-porch = <8>;
198 vsync-len = <2>;
199 hsync-active = <1>;
200 vsync-active = <0>;
201 de-active = <1>;
202 pixelclk-active = <1>;
203 interlaced;
204 doublescan;
205 doubleclk;
206 };
207 timing1: 480x800 {
208 clock-frequency = <9000000>;
209 hactive = <480>;
210 vactive = <800>;
211 hfront-porch = <10>;
212 hback-porch = <59>;
213 hsync-len = <12>;
214 vback-porch = <15>;
215 vfront-porch = <17>;
216 vsync-len = <16>;
217 hsync-active = <0>;
218 vsync-active = <1>;
219 de-active = <0>;
220 pixelclk-active = <0>;
221 };
222 timing2: 800x480 {
223 clock-frequency = <33500000>;
224 hactive = <800>;
225 vactive = <480>;
226 hback-porch = <89>;
227 hfront-porch = <164>;
228 vback-porch = <23>;
229 vfront-porch = <10>;
230 hsync-len = <11>;
231 vsync-len = <13>;
232 };
233 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700234 };
235
236 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600237 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700238 compatible = "not,compatible";
239 };
240
241 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600242 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700243 };
244
Simon Glass5620cf82018-10-01 12:22:40 -0600245 backlight: backlight {
246 compatible = "pwm-backlight";
247 enable-gpios = <&gpio_a 1>;
248 power-supply = <&ldo_1>;
249 pwms = <&pwm 0 1000>;
250 default-brightness-level = <5>;
251 brightness-levels = <0 16 32 64 128 170 202 234 255>;
252 };
253
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200254 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200255 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200256 bind-test-child1 {
257 compatible = "sandbox,phy";
258 #phy-cells = <1>;
259 };
260
261 bind-test-child2 {
262 compatible = "simple-bus";
263 };
264 };
265
Simon Glassb2c1cac2014-02-26 15:59:21 -0700266 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600267 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700268 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600269 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700270 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530271
272 mux-controls = <&muxcontroller0 0>;
273 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700274 };
275
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200276 phy_provider0: gen_phy@0 {
277 compatible = "sandbox,phy";
278 #phy-cells = <1>;
279 };
280
281 phy_provider1: gen_phy@1 {
282 compatible = "sandbox,phy";
283 #phy-cells = <0>;
284 broken;
285 };
286
developer71092972020-05-02 11:35:12 +0200287 phy_provider2: gen_phy@2 {
288 compatible = "sandbox,phy";
289 #phy-cells = <0>;
290 };
291
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200292 gen_phy_user: gen_phy_user {
293 compatible = "simple-bus";
294 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
295 phy-names = "phy1", "phy2", "phy3";
296 };
297
developer71092972020-05-02 11:35:12 +0200298 gen_phy_user1: gen_phy_user1 {
299 compatible = "simple-bus";
300 phys = <&phy_provider0 0>, <&phy_provider2>;
301 phy-names = "phy1", "phy2";
302 };
303
Simon Glassb2c1cac2014-02-26 15:59:21 -0700304 some-bus {
305 #address-cells = <1>;
306 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600307 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600308 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600309 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700310 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600311 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700312 compatible = "denx,u-boot-fdt-test";
313 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600314 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700315 ping-add = <5>;
316 };
Simon Glass40717422014-07-23 06:55:18 -0600317 c-test@0 {
318 compatible = "denx,u-boot-fdt-test";
319 reg = <0>;
320 ping-expect = <6>;
321 ping-add = <6>;
322 };
323 c-test@1 {
324 compatible = "denx,u-boot-fdt-test";
325 reg = <1>;
326 ping-expect = <7>;
327 ping-add = <7>;
328 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700329 };
330
331 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600332 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600333 ping-expect = <6>;
334 ping-add = <6>;
335 compatible = "google,another-fdt-test";
336 };
337
338 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600339 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600340 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700341 ping-add = <6>;
342 compatible = "google,another-fdt-test";
343 };
344
Simon Glass0ccb0972015-01-25 08:27:05 -0700345 f-test {
346 compatible = "denx,u-boot-fdt-test";
347 };
348
349 g-test {
350 compatible = "denx,u-boot-fdt-test";
351 };
352
Bin Mengd9d24782018-10-10 22:07:01 -0700353 h-test {
354 compatible = "denx,u-boot-fdt-test1";
355 };
356
developercf8bc132020-05-02 11:35:10 +0200357 i-test {
358 compatible = "mediatek,u-boot-fdt-test";
359 #address-cells = <1>;
360 #size-cells = <0>;
361
362 subnode@0 {
363 reg = <0>;
364 };
365
366 subnode@1 {
367 reg = <1>;
368 };
369
370 subnode@2 {
371 reg = <2>;
372 };
373 };
374
Simon Glass204675c2019-12-29 21:19:25 -0700375 devres-test {
376 compatible = "denx,u-boot-devres-test";
377 };
378
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530379 another-test {
380 reg = <0 2>;
381 compatible = "denx,u-boot-fdt-test";
382 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
383 test5-gpios = <&gpio_a 19>;
384 };
385
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100386 mmio-bus@0 {
387 #address-cells = <1>;
388 #size-cells = <1>;
389 compatible = "denx,u-boot-test-bus";
390 dma-ranges = <0x10000000 0x00000000 0x00040000>;
391
392 subnode@0 {
393 compatible = "denx,u-boot-fdt-test";
394 };
395 };
396
397 mmio-bus@1 {
398 #address-cells = <1>;
399 #size-cells = <1>;
400 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100401
402 subnode@0 {
403 compatible = "denx,u-boot-fdt-test";
404 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100405 };
406
Simon Glass3c601b12020-07-07 13:12:06 -0600407 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600408 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600409 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600410 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600411 child {
412 compatible = "denx,u-boot-acpi-test";
413 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600414 };
415
Simon Glass3c601b12020-07-07 13:12:06 -0600416 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600417 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600418 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600419 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600420 };
421
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200422 clocks {
423 clk_fixed: clk-fixed {
424 compatible = "fixed-clock";
425 #clock-cells = <0>;
426 clock-frequency = <1234>;
427 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000428
429 clk_fixed_factor: clk-fixed-factor {
430 compatible = "fixed-factor-clock";
431 #clock-cells = <0>;
432 clock-div = <3>;
433 clock-mult = <2>;
434 clocks = <&clk_fixed>;
435 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200436
437 osc {
438 compatible = "fixed-clock";
439 #clock-cells = <0>;
440 clock-frequency = <20000000>;
441 };
Stephen Warrena9622432016-06-17 09:44:00 -0600442 };
443
444 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600445 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600446 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200447 assigned-clocks = <&clk_sandbox 3>;
448 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600449 };
450
451 clk-test {
452 compatible = "sandbox,clk-test";
453 clocks = <&clk_fixed>,
454 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200455 <&clk_sandbox 0>,
456 <&clk_sandbox 3>,
457 <&clk_sandbox 2>;
458 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600459 };
460
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200461 ccf: clk-ccf {
462 compatible = "sandbox,clk-ccf";
463 };
464
Simon Glass5b968632015-05-22 15:42:15 -0600465 eth@10002000 {
466 compatible = "sandbox,eth";
467 reg = <0x10002000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500468 fake-host-hwaddr = [00 00 66 44 22 00];
Simon Glass5b968632015-05-22 15:42:15 -0600469 };
470
471 eth_5: eth@10003000 {
472 compatible = "sandbox,eth";
473 reg = <0x10003000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500474 fake-host-hwaddr = [00 00 66 44 22 11];
Simon Glass5b968632015-05-22 15:42:15 -0600475 };
476
Bin Meng04a11cb2015-08-27 22:25:53 -0700477 eth_3: sbe5 {
478 compatible = "sandbox,eth";
479 reg = <0x10005000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500480 fake-host-hwaddr = [00 00 66 44 22 33];
Bin Meng04a11cb2015-08-27 22:25:53 -0700481 };
482
Simon Glass5b968632015-05-22 15:42:15 -0600483 eth@10004000 {
484 compatible = "sandbox,eth";
485 reg = <0x10004000 0x1000>;
Joe Hershberger76f3c102018-07-02 14:47:45 -0500486 fake-host-hwaddr = [00 00 66 44 22 22];
Simon Glass5b968632015-05-22 15:42:15 -0600487 };
488
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800489 dsa_eth0: dsa-test-eth {
490 compatible = "sandbox,eth";
491 reg = <0x10006000 0x1000>;
492 fake-host-hwaddr = [00 00 66 44 22 66];
493 };
494
495 dsa-test {
496 compatible = "sandbox,dsa";
497
498 ports {
499 #address-cells = <1>;
500 #size-cells = <0>;
501 swp_0: port@0 {
502 reg = <0>;
503 label = "lan0";
504 phy-mode = "rgmii-rxid";
505
506 fixed-link {
507 speed = <100>;
508 full-duplex;
509 };
510 };
511
512 swp_1: port@1 {
513 reg = <1>;
514 label = "lan1";
515 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800516 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800517 };
518
519 port@2 {
520 reg = <2>;
521 ethernet = <&dsa_eth0>;
522
523 fixed-link {
524 speed = <1000>;
525 full-duplex;
526 };
527 };
528 };
529 };
530
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700531 firmware {
532 sandbox_firmware: sandbox-firmware {
533 compatible = "sandbox,firmware";
534 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200535
536 sandbox-scmi-agent@0 {
537 compatible = "sandbox,scmi-agent";
538 #address-cells = <1>;
539 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200540
541 clk_scmi0: protocol@14 {
542 reg = <0x14>;
543 #clock-cells = <1>;
544 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200545
546 reset_scmi0: protocol@16 {
547 reg = <0x16>;
548 #reset-cells = <1>;
549 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100550
551 protocol@17 {
552 reg = <0x17>;
553
554 regulators {
555 #address-cells = <1>;
556 #size-cells = <0>;
557
558 regul0_scmi0: reg@0 {
559 reg = <0>;
560 regulator-name = "sandbox-voltd0";
561 regulator-min-microvolt = <1100000>;
562 regulator-max-microvolt = <3300000>;
563 };
564 regul1_scmi0: reg@1 {
565 reg = <0x1>;
566 regulator-name = "sandbox-voltd1";
567 regulator-min-microvolt = <1800000>;
568 };
569 };
570 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200571 };
572
573 sandbox-scmi-agent@1 {
574 compatible = "sandbox,scmi-agent";
575 #address-cells = <1>;
576 #size-cells = <0>;
577
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200578 clk_scmi1: protocol@14 {
579 reg = <0x14>;
580 #clock-cells = <1>;
581 };
582
Etienne Carriere02fd1262020-09-09 18:44:00 +0200583 protocol@10 {
584 reg = <0x10>;
585 };
586 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700587 };
588
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100589 pinctrl-gpio {
590 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700591
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100592 gpio_a: base-gpios {
593 compatible = "sandbox,gpio";
594 gpio-controller;
595 #gpio-cells = <1>;
596 gpio-bank-name = "a";
597 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200598 hog_input_active_low {
599 gpio-hog;
600 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200601 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200602 };
603 hog_input_active_high {
604 gpio-hog;
605 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200606 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200607 };
608 hog_output_low {
609 gpio-hog;
610 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200611 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200612 };
613 hog_output_high {
614 gpio-hog;
615 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200616 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200617 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100618 };
619
620 gpio_b: extra-gpios {
621 compatible = "sandbox,gpio";
622 gpio-controller;
623 #gpio-cells = <5>;
624 gpio-bank-name = "b";
625 sandbox,gpio-count = <10>;
626 };
Simon Glass25348a42014-10-13 23:42:11 -0600627
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100628 gpio_c: pinmux-gpios {
629 compatible = "sandbox,gpio";
630 gpio-controller;
631 #gpio-cells = <2>;
632 gpio-bank-name = "c";
633 sandbox,gpio-count = <10>;
634 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100635 };
636
Simon Glass7df766e2014-12-10 08:55:55 -0700637 i2c@0 {
638 #address-cells = <1>;
639 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600640 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700641 compatible = "sandbox,i2c";
642 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200643 pinctrl-names = "default";
644 pinctrl-0 = <&pinmux_i2c0_pins>;
645
Simon Glass7df766e2014-12-10 08:55:55 -0700646 eeprom@2c {
647 reg = <0x2c>;
648 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700649 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200650 partitions {
651 compatible = "fixed-partitions";
652 #address-cells = <1>;
653 #size-cells = <1>;
654 bootcount_i2c: bootcount@10 {
655 reg = <10 2>;
656 };
657 };
Simon Glass7df766e2014-12-10 08:55:55 -0700658 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200659
Simon Glass336b2952015-05-22 15:42:17 -0600660 rtc_0: rtc@43 {
661 reg = <0x43>;
662 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700663 sandbox,emul = <&emul0>;
Simon Glass336b2952015-05-22 15:42:17 -0600664 };
665
666 rtc_1: rtc@61 {
667 reg = <0x61>;
668 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700669 sandbox,emul = <&emul1>;
670 };
671
672 i2c_emul: emul {
673 reg = <0xff>;
674 compatible = "sandbox,i2c-emul-parent";
675 emul_eeprom: emul-eeprom {
676 compatible = "sandbox,i2c-eeprom";
677 sandbox,filename = "i2c.bin";
678 sandbox,size = <256>;
679 };
680 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700681 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700682 };
683 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700684 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600685 };
686 };
687
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200688 sandbox_pmic: sandbox_pmic {
689 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700690 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200691 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200692
693 mc34708: pmic@41 {
694 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700695 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200696 };
Simon Glass7df766e2014-12-10 08:55:55 -0700697 };
698
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100699 bootcount@0 {
700 compatible = "u-boot,bootcount-rtc";
701 rtc = <&rtc_1>;
702 offset = <0x13>;
703 };
704
Michal Simek4f18f922020-05-28 11:48:55 +0200705 bootcount {
706 compatible = "u-boot,bootcount-i2c-eeprom";
707 i2c-eeprom = <&bootcount_i2c>;
708 };
709
Marek Szyprowskiad398592021-02-18 11:33:18 +0100710 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100711 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100712 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100713 vdd-supply = <&buck2>;
714 vss-microvolts = <0>;
715 };
716
Simon Glass515dcff2020-02-06 09:55:00 -0700717 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700718 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700719 interrupt-controller;
720 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700721 };
722
Simon Glass90b6fef2016-01-18 19:52:26 -0700723 lcd {
724 u-boot,dm-pre-reloc;
725 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200726 pinctrl-names = "default";
727 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700728 xres = <1366>;
729 yres = <768>;
730 };
731
Simon Glassd783eb32015-07-06 12:54:34 -0600732 leds {
733 compatible = "gpio-leds";
734
735 iracibble {
736 gpios = <&gpio_a 1 0>;
737 label = "sandbox:red";
738 };
739
740 martinet {
741 gpios = <&gpio_a 2 0>;
742 label = "sandbox:green";
743 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200744
745 default_on {
746 gpios = <&gpio_a 5 0>;
747 label = "sandbox:default_on";
748 default-state = "on";
749 };
750
751 default_off {
752 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400753 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200754 default-state = "off";
755 };
Simon Glassd783eb32015-07-06 12:54:34 -0600756 };
757
Stephen Warren62f2c902016-05-16 17:41:37 -0600758 mbox: mbox {
759 compatible = "sandbox,mbox";
760 #mbox-cells = <1>;
761 };
762
763 mbox-test {
764 compatible = "sandbox,mbox-test";
765 mboxes = <&mbox 100>, <&mbox 1>;
766 mbox-names = "other", "test";
767 };
768
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900769 cpus {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400770 timebase-frequency = <2000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900771 cpu-test1 {
Sean Anderson79d3bba2020-09-28 10:52:23 -0400772 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900773 compatible = "sandbox,cpu_sandbox";
774 u-boot,dm-pre-reloc;
775 };
Mario Sixdea5df72018-08-06 10:23:44 +0200776
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900777 cpu-test2 {
778 compatible = "sandbox,cpu_sandbox";
779 u-boot,dm-pre-reloc;
780 };
Mario Sixdea5df72018-08-06 10:23:44 +0200781
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900782 cpu-test3 {
783 compatible = "sandbox,cpu_sandbox";
784 u-boot,dm-pre-reloc;
785 };
Mario Sixdea5df72018-08-06 10:23:44 +0200786 };
787
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500788 chipid: chipid {
789 compatible = "sandbox,soc";
790 };
791
Simon Glassc953aaf2018-12-10 10:37:34 -0700792 i2s: i2s {
793 compatible = "sandbox,i2s";
794 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700795 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700796 };
797
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200798 nop-test_0 {
799 compatible = "sandbox,nop_sandbox1";
800 nop-test_1 {
801 compatible = "sandbox,nop_sandbox2";
802 bind = "True";
803 };
804 nop-test_2 {
805 compatible = "sandbox,nop_sandbox2";
806 bind = "False";
807 };
808 };
809
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200810 misc-test {
811 compatible = "sandbox,misc_sandbox";
812 };
813
Simon Glasse4fef742017-04-23 20:02:07 -0600814 mmc2 {
815 compatible = "sandbox,mmc";
816 };
817
818 mmc1 {
819 compatible = "sandbox,mmc";
820 };
821
822 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600823 compatible = "sandbox,mmc";
824 };
825
Simon Glass53a68b32019-02-16 20:24:50 -0700826 pch {
827 compatible = "sandbox,pch";
828 };
829
Tom Rini4a3ca482020-02-11 12:41:23 -0500830 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700831 compatible = "sandbox,pci";
832 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500833 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700834 #address-cells = <3>;
835 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600836 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700837 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700838 pci@0,0 {
839 compatible = "pci-generic";
840 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600841 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700842 };
Alex Margineanf1274432019-06-07 11:24:24 +0300843 pci@1,0 {
844 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600845 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
846 reg = <0x02000814 0 0 0 0
847 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600848 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300849 };
Simon Glass937bb472019-12-06 21:41:57 -0700850 p2sb-pci@2,0 {
851 compatible = "sandbox,p2sb";
852 reg = <0x02001010 0 0 0 0>;
853 sandbox,emul = <&p2sb_emul>;
854
855 adder {
856 intel,p2sb-port-id = <3>;
857 compatible = "sandbox,adder";
858 };
859 };
Simon Glass8c501022019-12-06 21:41:54 -0700860 pci@1e,0 {
861 compatible = "sandbox,pmc";
862 reg = <0xf000 0 0 0 0>;
863 sandbox,emul = <&pmc_emul1e>;
864 acpi-base = <0x400>;
865 gpe0-dwx-mask = <0xf>;
866 gpe0-dwx-shift-base = <4>;
867 gpe0-dw = <6 7 9>;
868 gpe0-sts = <0x20>;
869 gpe0-en = <0x30>;
870 };
Simon Glass3a6eae62015-03-05 12:25:34 -0700871 pci@1f,0 {
872 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600873 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
874 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600875 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700876 };
877 };
878
Simon Glassb98ba4c2019-09-25 08:56:10 -0600879 pci-emul0 {
880 compatible = "sandbox,pci-emul-parent";
881 swap_case_emul0_0: emul0@0,0 {
882 compatible = "sandbox,swap-case";
883 };
884 swap_case_emul0_1: emul0@1,0 {
885 compatible = "sandbox,swap-case";
886 use-ea;
887 };
888 swap_case_emul0_1f: emul0@1f,0 {
889 compatible = "sandbox,swap-case";
890 };
Simon Glass937bb472019-12-06 21:41:57 -0700891 p2sb_emul: emul@2,0 {
892 compatible = "sandbox,p2sb-emul";
893 };
Simon Glass8c501022019-12-06 21:41:54 -0700894 pmc_emul1e: emul@1e,0 {
895 compatible = "sandbox,pmc-emul";
896 };
Simon Glassb98ba4c2019-09-25 08:56:10 -0600897 };
898
Tom Rini4a3ca482020-02-11 12:41:23 -0500899 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -0700900 compatible = "sandbox,pci";
901 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500902 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -0700903 #address-cells = <3>;
904 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -0700905 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
906 0x02000000 0 0x31000000 0x31000000 0 0x2000 // MEM1
907 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -0700908 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +0200909 0x0c 0x00 0x1234 0x5678
910 0x10 0x00 0x1234 0x5678>;
911 pci@10,0 {
912 reg = <0x8000 0 0 0 0>;
913 };
Bin Meng408e5902018-08-03 01:14:41 -0700914 };
915
Tom Rini4a3ca482020-02-11 12:41:23 -0500916 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -0700917 compatible = "sandbox,pci";
918 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500919 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -0700920 #address-cells = <3>;
921 #size-cells = <2>;
922 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
923 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
924 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
925 pci@1f,0 {
926 compatible = "pci-generic";
927 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600928 sandbox,emul = <&swap_case_emul2_1f>;
929 };
930 };
931
932 pci-emul2 {
933 compatible = "sandbox,pci-emul-parent";
934 swap_case_emul2_1f: emul2@1f,0 {
935 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -0700936 };
937 };
938
Ramon Friedc64f19b2019-04-27 11:15:23 +0300939 pci_ep: pci_ep {
940 compatible = "sandbox,pci_ep";
941 };
942
Simon Glass9c433fe2017-04-23 20:10:44 -0600943 probing {
944 compatible = "simple-bus";
945 test1 {
946 compatible = "denx,u-boot-probe-test";
947 };
948
949 test2 {
950 compatible = "denx,u-boot-probe-test";
951 };
952
953 test3 {
954 compatible = "denx,u-boot-probe-test";
955 };
956
957 test4 {
958 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +0100959 first-syscon = <&syscon0>;
960 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +0100961 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -0600962 };
963 };
964
Stephen Warren92c67fa2016-07-13 13:45:31 -0600965 pwrdom: power-domain {
966 compatible = "sandbox,power-domain";
967 #power-domain-cells = <1>;
968 };
969
970 power-domain-test {
971 compatible = "sandbox,power-domain-test";
972 power-domains = <&pwrdom 2>;
973 };
974
Simon Glass5620cf82018-10-01 12:22:40 -0600975 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -0600976 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600977 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200978 pinctrl-names = "default";
979 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600980 };
981
982 pwm2 {
983 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -0600984 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -0600985 };
986
Simon Glass3d355e62015-07-06 12:54:31 -0600987 ram {
988 compatible = "sandbox,ram";
989 };
990
Simon Glassd860f222015-07-06 12:54:29 -0600991 reset@0 {
992 compatible = "sandbox,warm-reset";
993 };
994
995 reset@1 {
996 compatible = "sandbox,reset";
997 };
998
Stephen Warren6488e642016-06-17 09:43:59 -0600999 resetc: reset-ctl {
1000 compatible = "sandbox,reset-ctl";
1001 #reset-cells = <1>;
1002 };
1003
1004 reset-ctl-test {
1005 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001006 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1007 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001008 };
1009
Sughosh Ganu23e37512019-12-28 23:58:31 +05301010 rng {
1011 compatible = "sandbox,sandbox-rng";
1012 };
1013
Nishanth Menonedf85812015-09-17 15:42:41 -05001014 rproc_1: rproc@1 {
1015 compatible = "sandbox,test-processor";
1016 remoteproc-name = "remoteproc-test-dev1";
1017 };
1018
1019 rproc_2: rproc@2 {
1020 compatible = "sandbox,test-processor";
1021 internal-memory-mapped;
1022 remoteproc-name = "remoteproc-test-dev2";
1023 };
1024
Simon Glass5620cf82018-10-01 12:22:40 -06001025 panel {
1026 compatible = "simple-panel";
1027 backlight = <&backlight 0 100>;
1028 };
1029
Ramon Fried26ed32e2018-07-02 02:57:59 +03001030 smem@0 {
1031 compatible = "sandbox,smem";
1032 };
1033
Simon Glass76072ac2018-12-10 10:37:36 -07001034 sound {
1035 compatible = "sandbox,sound";
1036 cpu {
1037 sound-dai = <&i2s 0>;
1038 };
1039
1040 codec {
1041 sound-dai = <&audio 0>;
1042 };
1043 };
1044
Simon Glass25348a42014-10-13 23:42:11 -06001045 spi@0 {
1046 #address-cells = <1>;
1047 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001048 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001049 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001050 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001051 pinctrl-names = "default";
1052 pinctrl-0 = <&pinmux_spi0_pins>;
1053
Simon Glass25348a42014-10-13 23:42:11 -06001054 spi.bin@0 {
1055 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001056 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001057 spi-max-frequency = <40000000>;
1058 sandbox,filename = "spi.bin";
1059 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001060 spi.bin@1 {
1061 reg = <1>;
1062 compatible = "spansion,m25p16", "jedec,spi-nor";
1063 spi-max-frequency = <50000000>;
1064 sandbox,filename = "spi.bin";
1065 spi-cpol;
1066 spi-cpha;
1067 };
Simon Glass25348a42014-10-13 23:42:11 -06001068 };
1069
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001070 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001071 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001072 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001073 };
1074
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001075 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001076 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001077 reg = <0x20 5
1078 0x28 6
1079 0x30 7
1080 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001081 };
1082
Patrick Delaunayee010432019-03-07 09:57:13 +01001083 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001084 compatible = "simple-mfd", "syscon";
1085 reg = <0x40 5
1086 0x48 6
1087 0x50 7
1088 0x58 8>;
1089 };
1090
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301091 syscon3: syscon@3 {
1092 compatible = "simple-mfd", "syscon";
1093 reg = <0x000100 0x10>;
1094
1095 muxcontroller0: a-mux-controller {
1096 compatible = "mmio-mux";
1097 #mux-control-cells = <1>;
1098
1099 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1100 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1101 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1102 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1103 u-boot,mux-autoprobe;
1104 };
1105 };
1106
1107 muxcontroller1: emul-mux-controller {
1108 compatible = "mux-emul";
1109 #mux-control-cells = <0>;
1110 u-boot,mux-autoprobe;
1111 idle-state = <0xabcd>;
1112 };
1113
Simon Glass791a17f2020-12-16 21:20:27 -07001114 testfdtm0 {
1115 compatible = "denx,u-boot-fdtm-test";
1116 };
1117
1118 testfdtm1: testfdtm1 {
1119 compatible = "denx,u-boot-fdtm-test";
1120 };
1121
1122 testfdtm2 {
1123 compatible = "denx,u-boot-fdtm-test";
1124 };
1125
Sean Anderson79d3bba2020-09-28 10:52:23 -04001126 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001127 compatible = "sandbox,timer";
1128 clock-frequency = <1000000>;
1129 };
1130
Sean Anderson79d3bba2020-09-28 10:52:23 -04001131 timer@1 {
1132 compatible = "sandbox,timer";
1133 sandbox,timebase-frequency-fallback;
1134 };
1135
Miquel Raynal80938c12018-05-15 11:57:27 +02001136 tpm2 {
1137 compatible = "sandbox,tpm2";
1138 };
1139
Simon Glass5b968632015-05-22 15:42:15 -06001140 uart0: serial {
1141 compatible = "sandbox,serial";
1142 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001143 pinctrl-names = "default";
1144 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001145 };
1146
Simon Glass31680482015-03-25 12:23:05 -06001147 usb_0: usb@0 {
1148 compatible = "sandbox,usb";
1149 status = "disabled";
1150 hub {
1151 compatible = "sandbox,usb-hub";
1152 #address-cells = <1>;
1153 #size-cells = <0>;
1154 flash-stick {
1155 reg = <0>;
1156 compatible = "sandbox,usb-flash";
1157 };
1158 };
1159 };
1160
1161 usb_1: usb@1 {
1162 compatible = "sandbox,usb";
1163 hub {
1164 compatible = "usb-hub";
1165 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001166 #address-cells = <1>;
1167 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001168 hub-emul {
1169 compatible = "sandbox,usb-hub";
1170 #address-cells = <1>;
1171 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001172 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001173 reg = <0>;
1174 compatible = "sandbox,usb-flash";
1175 sandbox,filepath = "testflash.bin";
1176 };
1177
Simon Glass4700fe52015-11-08 23:48:01 -07001178 flash-stick@1 {
1179 reg = <1>;
1180 compatible = "sandbox,usb-flash";
1181 sandbox,filepath = "testflash1.bin";
1182 };
1183
1184 flash-stick@2 {
1185 reg = <2>;
1186 compatible = "sandbox,usb-flash";
1187 sandbox,filepath = "testflash2.bin";
1188 };
1189
Simon Glassc0ccc722015-11-08 23:48:08 -07001190 keyb@3 {
1191 reg = <3>;
1192 compatible = "sandbox,usb-keyb";
1193 };
1194
Simon Glass31680482015-03-25 12:23:05 -06001195 };
Michael Walle7c961322020-06-02 01:47:07 +02001196
1197 usbstor@1 {
1198 reg = <1>;
1199 };
1200 usbstor@3 {
1201 reg = <3>;
1202 };
Simon Glass31680482015-03-25 12:23:05 -06001203 };
1204 };
1205
1206 usb_2: usb@2 {
1207 compatible = "sandbox,usb";
1208 status = "disabled";
1209 };
1210
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001211 spmi: spmi@0 {
1212 compatible = "sandbox,spmi";
1213 #address-cells = <0x1>;
1214 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001215 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001216 pm8916@0 {
1217 compatible = "qcom,spmi-pmic";
1218 reg = <0x0 0x1>;
1219 #address-cells = <0x1>;
1220 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001221 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001222
1223 spmi_gpios: gpios@c000 {
1224 compatible = "qcom,pm8916-gpio";
1225 reg = <0xc000 0x400>;
1226 gpio-controller;
1227 gpio-count = <4>;
1228 #gpio-cells = <2>;
1229 gpio-bank-name="spmi";
1230 };
1231 };
1232 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001233
1234 wdt0: wdt@0 {
1235 compatible = "sandbox,wdt";
1236 };
Rob Clarka471b672018-01-10 11:33:30 +01001237
Mario Six95922152018-08-09 14:51:19 +02001238 axi: axi@0 {
1239 compatible = "sandbox,axi";
1240 #address-cells = <0x1>;
1241 #size-cells = <0x1>;
1242 store@0 {
1243 compatible = "sandbox,sandbox_store";
1244 reg = <0x0 0x400>;
1245 };
1246 };
1247
Rob Clarka471b672018-01-10 11:33:30 +01001248 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001249 #address-cells = <1>;
1250 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001251 setting = "sunrise ohoka";
1252 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001253 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001254 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001255 chosen-test {
1256 compatible = "denx,u-boot-fdt-test";
1257 reg = <9 1>;
1258 };
1259 };
Mario Six35616ef2018-03-12 14:53:33 +01001260
1261 translation-test@8000 {
1262 compatible = "simple-bus";
1263 reg = <0x8000 0x4000>;
1264
1265 #address-cells = <0x2>;
1266 #size-cells = <0x1>;
1267
1268 ranges = <0 0x0 0x8000 0x1000
1269 1 0x100 0x9000 0x1000
1270 2 0x200 0xA000 0x1000
1271 3 0x300 0xB000 0x1000
1272 >;
1273
Fabien Dessenne22236e02019-05-31 15:11:30 +02001274 dma-ranges = <0 0x000 0x10000000 0x1000
1275 1 0x100 0x20000000 0x1000
1276 >;
1277
Mario Six35616ef2018-03-12 14:53:33 +01001278 dev@0,0 {
1279 compatible = "denx,u-boot-fdt-dummy";
1280 reg = <0 0x0 0x1000>;
Álvaro Fernández Rojasa3181152018-12-03 19:37:09 +01001281 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001282 };
1283
1284 dev@1,100 {
1285 compatible = "denx,u-boot-fdt-dummy";
1286 reg = <1 0x100 0x1000>;
1287
1288 };
1289
1290 dev@2,200 {
1291 compatible = "denx,u-boot-fdt-dummy";
1292 reg = <2 0x200 0x1000>;
1293 };
1294
1295
1296 noxlatebus@3,300 {
1297 compatible = "simple-bus";
1298 reg = <3 0x300 0x1000>;
1299
1300 #address-cells = <0x1>;
1301 #size-cells = <0x0>;
1302
1303 dev@42 {
1304 compatible = "denx,u-boot-fdt-dummy";
1305 reg = <0x42>;
1306 };
1307 };
1308 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001309
1310 osd {
1311 compatible = "sandbox,sandbox_osd";
1312 };
Tom Rinib93eea72018-09-30 18:16:51 -04001313
Jens Wiklander86afaa62018-09-25 16:40:16 +02001314 sandbox_tee {
1315 compatible = "sandbox,tee";
1316 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001317
1318 sandbox_virtio1 {
1319 compatible = "sandbox,virtio1";
1320 };
1321
1322 sandbox_virtio2 {
1323 compatible = "sandbox,virtio2";
1324 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001325
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001326 sandbox_scmi {
1327 compatible = "sandbox,scmi-devices";
1328 clocks = <&clk_scmi0 7>, <&clk_scmi0 3>, <&clk_scmi1 1>;
Etienne Carriere8b9b6892020-09-09 18:44:07 +02001329 resets = <&reset_scmi0 3>;
Etienne Carriereb8f15cd2021-03-08 22:38:07 +01001330 regul0-supply = <&regul0_scmi0>;
1331 regul1-supply = <&regul1_scmi0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001332 };
1333
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001334 pinctrl {
1335 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001336
Sean Anderson3438e3b2020-09-14 11:01:57 -04001337 pinctrl-names = "default", "alternate";
1338 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1339 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001340
Sean Anderson3438e3b2020-09-14 11:01:57 -04001341 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001342 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001343 pins = "P5";
1344 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001345 bias-pull-up;
1346 input-disable;
1347 };
1348 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001349 pins = "P6";
1350 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001351 output-high;
1352 drive-open-drain;
1353 };
1354 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001355 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001356 bias-pull-down;
1357 input-enable;
1358 };
1359 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001360 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001361 bias-disable;
1362 };
1363 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001364
1365 pinctrl_i2c: i2c {
1366 groups {
1367 groups = "I2C_UART";
1368 function = "I2C";
1369 };
1370
1371 pins {
1372 pins = "P0", "P1";
1373 drive-open-drain;
1374 };
1375 };
1376
1377 pinctrl_i2s: i2s {
1378 groups = "SPI_I2S";
1379 function = "I2S";
1380 };
1381
1382 pinctrl_spi: spi {
1383 groups = "SPI_I2S";
1384 function = "SPI";
1385
1386 cs {
1387 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1388 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1389 };
1390 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001391 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001392
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001393 pinctrl-single-no-width {
1394 compatible = "pinctrl-single";
1395 reg = <0x0000 0x238>;
1396 #pinctrl-cells = <1>;
1397 pinctrl-single,function-mask = <0x7f>;
1398 };
1399
1400 pinctrl-single-pins {
1401 compatible = "pinctrl-single";
1402 reg = <0x0000 0x238>;
1403 #pinctrl-cells = <1>;
1404 pinctrl-single,register-width = <32>;
1405 pinctrl-single,function-mask = <0x7f>;
1406
1407 pinmux_pwm_pins: pinmux_pwm_pins {
1408 pinctrl-single,pins = < 0x48 0x06 >;
1409 };
1410
1411 pinmux_spi0_pins: pinmux_spi0_pins {
1412 pinctrl-single,pins = <
1413 0x190 0x0c
1414 0x194 0x0c
1415 0x198 0x23
1416 0x19c 0x0c
1417 >;
1418 };
1419
1420 pinmux_uart0_pins: pinmux_uart0_pins {
1421 pinctrl-single,pins = <
1422 0x70 0x30
1423 0x74 0x00
1424 >;
1425 };
1426 };
1427
1428 pinctrl-single-bits {
1429 compatible = "pinctrl-single";
1430 reg = <0x0000 0x50>;
1431 #pinctrl-cells = <2>;
1432 pinctrl-single,bit-per-mux;
1433 pinctrl-single,register-width = <32>;
1434 pinctrl-single,function-mask = <0xf>;
1435
1436 pinmux_i2c0_pins: pinmux_i2c0_pins {
1437 pinctrl-single,bits = <
1438 0x10 0x00002200 0x0000ff00
1439 >;
1440 };
1441
1442 pinmux_lcd_pins: pinmux_lcd_pins {
1443 pinctrl-single,bits = <
1444 0x40 0x22222200 0xffffff00
1445 0x44 0x22222222 0xffffffff
1446 0x48 0x00000022 0x000000ff
1447 0x48 0x02000000 0x0f000000
1448 0x4c 0x02000022 0x0f0000ff
1449 >;
1450 };
1451 };
1452
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001453 hwspinlock@0 {
1454 compatible = "sandbox,hwspinlock";
1455 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001456
1457 dma: dma {
1458 compatible = "sandbox,dma";
1459 #dma-cells = <1>;
1460
1461 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1462 dma-names = "m2m", "tx0", "rx0";
1463 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001464
Alex Marginean0649be52019-07-12 10:13:53 +03001465 /*
1466 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1467 * end of the test. If parent mdio is removed first, clean-up of the
1468 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1469 * active at the end of the test. That it turn doesn't allow the mdio
1470 * class to be destroyed, triggering an error.
1471 */
1472 mdio-mux-test {
1473 compatible = "sandbox,mdio-mux";
1474 #address-cells = <1>;
1475 #size-cells = <0>;
1476 mdio-parent-bus = <&mdio>;
1477
1478 mdio-ch-test@0 {
1479 reg = <0>;
1480 };
1481 mdio-ch-test@1 {
1482 reg = <1>;
1483 };
1484 };
1485
1486 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001487 compatible = "sandbox,mdio";
1488 };
Sean Andersonb7860542020-06-24 06:41:12 -04001489
1490 pm-bus-test {
1491 compatible = "simple-pm-bus";
1492 clocks = <&clk_sandbox 4>;
1493 power-domains = <&pwrdom 1>;
1494 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001495
1496 resetc2: syscon-reset {
1497 compatible = "syscon-reset";
1498 #reset-cells = <1>;
1499 regmap = <&syscon0>;
1500 offset = <1>;
1501 mask = <0x27FFFFFF>;
1502 assert-high = <0>;
1503 };
1504
1505 syscon-reset-test {
1506 compatible = "sandbox,misc_sandbox";
1507 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1508 reset-names = "valid", "no_mask", "out_of_range";
1509 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301510
Simon Glass458b66a2020-11-05 06:32:05 -07001511 sysinfo {
1512 compatible = "sandbox,sysinfo-sandbox";
1513 };
1514
Sean Anderson1c830672021-04-20 10:50:58 -04001515 sysinfo-gpio {
1516 compatible = "gpio-sysinfo";
1517 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1518 revisions = <19>, <5>;
1519 names = "rev_a", "foo";
1520 };
1521
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301522 some_regmapped-bus {
1523 #address-cells = <0x1>;
1524 #size-cells = <0x1>;
1525
1526 ranges = <0x0 0x0 0x10>;
1527 compatible = "simple-bus";
1528
1529 regmap-test_0 {
1530 reg = <0 0x10>;
1531 compatible = "sandbox,regmap_test";
1532 };
1533 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001534};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001535
1536#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001537#include "cros-ec-keyboard.dtsi"