Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
wdenk | 67ff36c | 2002-11-19 23:01:07 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2002 |
Albert ARIBAUD | 60fbc8d | 2011-08-04 18:45:45 +0200 | [diff] [blame] | 4 | * Daniel Engström, Omicron Ceti AB, daniel@omicron.se |
wdenk | 67ff36c | 2002-11-19 23:01:07 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __ASM_PROCESSOR_H_ |
| 8 | #define __ASM_PROCESSOR_H_ 1 |
Graeme Russ | 25391d1 | 2011-02-12 15:11:30 +1100 | [diff] [blame] | 9 | |
Simon Glass | 9fc71c1 | 2014-11-14 20:56:29 -0700 | [diff] [blame] | 10 | #define X86_GDT_ENTRY_SIZE 8 |
Graeme Russ | 391bb95 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 11 | |
Simon Glass | 9fc71c1 | 2014-11-14 20:56:29 -0700 | [diff] [blame] | 12 | #define X86_GDT_ENTRY_NULL 0 |
| 13 | #define X86_GDT_ENTRY_UNUSED 1 |
| 14 | #define X86_GDT_ENTRY_32BIT_CS 2 |
| 15 | #define X86_GDT_ENTRY_32BIT_DS 3 |
| 16 | #define X86_GDT_ENTRY_32BIT_FS 4 |
| 17 | #define X86_GDT_ENTRY_16BIT_CS 5 |
| 18 | #define X86_GDT_ENTRY_16BIT_DS 6 |
| 19 | #define X86_GDT_ENTRY_16BIT_FLAT_CS 7 |
| 20 | #define X86_GDT_ENTRY_16BIT_FLAT_DS 8 |
| 21 | #define X86_GDT_NUM_ENTRIES 9 |
Graeme Russ | 391bb95 | 2011-12-31 10:24:36 +1100 | [diff] [blame] | 22 | |
| 23 | #define X86_GDT_SIZE (X86_GDT_NUM_ENTRIES * X86_GDT_ENTRY_SIZE) |
Graeme Russ | 25391d1 | 2011-02-12 15:11:30 +1100 | [diff] [blame] | 24 | |
Simon Glass | a9a4426 | 2015-04-29 22:25:59 -0600 | [diff] [blame] | 25 | /* Length of the public header on Intel microcode blobs */ |
| 26 | #define UCODE_HEADER_LEN 0x30 |
| 27 | |
Simon Glass | be36df6 | 2014-11-10 18:00:24 -0700 | [diff] [blame] | 28 | #ifndef __ASSEMBLY__ |
| 29 | |
Simon Glass | e0e7bd0 | 2015-04-28 20:11:29 -0600 | [diff] [blame] | 30 | /* |
| 31 | * This register is documented in (for example) the Intel Atom Processor E3800 |
| 32 | * Product Family Datasheet in "PCU - Power Management Controller (PMC)". |
| 33 | * |
| 34 | * RST_CNT: Reset Control Register (RST_CNT) Offset cf9. |
| 35 | * |
| 36 | * The naming follows Intel's naming. |
| 37 | */ |
Simon Glass | 8b73e9f | 2016-03-11 22:06:59 -0700 | [diff] [blame] | 38 | #define IO_PORT_RESET 0xcf9 |
Simon Glass | f226c41 | 2014-11-12 22:42:19 -0700 | [diff] [blame] | 39 | |
Simon Glass | e0e7bd0 | 2015-04-28 20:11:29 -0600 | [diff] [blame] | 40 | enum { |
| 41 | SYS_RST = 1 << 1, /* 0 for soft reset, 1 for hard reset */ |
| 42 | RST_CPU = 1 << 2, /* initiate reset */ |
| 43 | FULL_RST = 1 << 3, /* full power cycle */ |
| 44 | }; |
| 45 | |
| 46 | /** |
| 47 | * x86_full_reset() - reset everything: perform a full power cycle |
| 48 | */ |
| 49 | void x86_full_reset(void); |
| 50 | |
Simon Glass | be36df6 | 2014-11-10 18:00:24 -0700 | [diff] [blame] | 51 | static inline __attribute__((always_inline)) void cpu_hlt(void) |
| 52 | { |
| 53 | asm("hlt"); |
| 54 | } |
| 55 | |
| 56 | static inline ulong cpu_get_sp(void) |
| 57 | { |
| 58 | ulong result; |
| 59 | |
| 60 | asm volatile( |
| 61 | "mov %%esp, %%eax" |
| 62 | : "=a" (result)); |
| 63 | return result; |
| 64 | } |
| 65 | |
| 66 | #endif /* __ASSEMBLY__ */ |
| 67 | |
wdenk | 67ff36c | 2002-11-19 23:01:07 +0000 | [diff] [blame] | 68 | #endif |