blob: 8bb7e16f94405e32224ef6d91130804d8bb4152f [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Marek Vasut3066a062017-09-15 21:13:55 +02002/*
3 * Pin Control driver for SuperH Pin Function Controller.
4 *
5 * Authors: Magnus Damm, Paul Mundt, Laurent Pinchart
6 *
7 * Copyright (C) 2008 Magnus Damm
8 * Copyright (C) 2009 - 2012 Paul Mundt
9 * Copyright (C) 2017 Marek Vasut
Marek Vasut3066a062017-09-15 21:13:55 +020010 */
11
12#define DRV_NAME "sh-pfc"
13
14#include <common.h>
15#include <dm.h>
16#include <errno.h>
Simon Glass9bc15642020-02-03 07:36:16 -070017#include <dm/device_compat.h>
Simon Glassd66c5f72020-02-03 07:36:15 -070018#include <dm/devres.h>
Marek Vasut3066a062017-09-15 21:13:55 +020019#include <dm/pinctrl.h>
Simon Glass4dcacfc2020-05-10 11:40:13 -060020#include <linux/bitops.h>
Simon Glassc06c1be2020-05-10 11:40:08 -060021#include <linux/bug.h>
Marek Vasut3066a062017-09-15 21:13:55 +020022#include <linux/io.h>
23#include <linux/sizes.h>
24
25#include "sh_pfc.h"
26
Marek Vasut3066a062017-09-15 21:13:55 +020027enum sh_pfc_model {
Marek Vasutc40f2d62018-01-17 22:18:59 +010028 SH_PFC_R8A7790 = 0,
Marek Vasut06ef9e82018-01-17 17:14:45 +010029 SH_PFC_R8A7791,
Marek Vasut1ef39302018-01-17 22:29:50 +010030 SH_PFC_R8A7792,
Marek Vasut06ef9e82018-01-17 17:14:45 +010031 SH_PFC_R8A7793,
Marek Vasut4dd88d52018-01-17 22:33:59 +010032 SH_PFC_R8A7794,
Marek Vasutc40f2d62018-01-17 22:18:59 +010033 SH_PFC_R8A7795,
Marek Vasut3066a062017-09-15 21:13:55 +020034 SH_PFC_R8A7796,
Adam Ford96980fb2020-06-30 09:30:09 -050035 SH_PFC_R8A774A1,
Biju Dasd1d78882020-10-28 10:34:21 +000036 SH_PFC_R8A774B1,
Biju Das121bd002020-10-28 10:34:22 +000037 SH_PFC_R8A774E1,
Marek Vasut72269e02019-03-04 01:32:44 +010038 SH_PFC_R8A77965,
Marek Vasuta0e11e52017-10-09 20:57:29 +020039 SH_PFC_R8A77970,
Marek Vasuta6a7f482019-07-29 19:59:44 +020040 SH_PFC_R8A77980,
Marek Vasut68a77042018-04-26 13:09:20 +020041 SH_PFC_R8A77990,
Marek Vasut7d35e642017-10-08 20:57:37 +020042 SH_PFC_R8A77995,
Marek Vasut3066a062017-09-15 21:13:55 +020043};
44
45struct sh_pfc_pin_config {
46 u32 type;
47};
48
49struct sh_pfc_pinctrl {
50 struct sh_pfc *pfc;
51
52 struct sh_pfc_pin_config *configs;
Marek Vasut3066a062017-09-15 21:13:55 +020053};
54
55struct sh_pfc_pin_range {
56 u16 start;
57 u16 end;
58};
59
60struct sh_pfc_pinctrl_priv {
61 struct sh_pfc pfc;
62 struct sh_pfc_pinctrl pmx;
63};
64
65int sh_pfc_get_pin_index(struct sh_pfc *pfc, unsigned int pin)
66{
67 unsigned int offset;
68 unsigned int i;
69
70 for (i = 0, offset = 0; i < pfc->nr_ranges; ++i) {
71 const struct sh_pfc_pin_range *range = &pfc->ranges[i];
72
73 if (pin <= range->end)
74 return pin >= range->start
75 ? offset + pin - range->start : -1;
76
77 offset += range->end - range->start + 1;
78 }
79
80 return -EINVAL;
81}
82
83static int sh_pfc_enum_in_range(u16 enum_id, const struct pinmux_range *r)
84{
85 if (enum_id < r->begin)
86 return 0;
87
88 if (enum_id > r->end)
89 return 0;
90
91 return 1;
92}
93
94u32 sh_pfc_read_raw_reg(void __iomem *mapped_reg, unsigned int reg_width)
95{
96 switch (reg_width) {
97 case 8:
98 return readb(mapped_reg);
99 case 16:
100 return readw(mapped_reg);
101 case 32:
102 return readl(mapped_reg);
103 }
104
105 BUG();
106 return 0;
107}
108
109void sh_pfc_write_raw_reg(void __iomem *mapped_reg, unsigned int reg_width,
110 u32 data)
111{
112 switch (reg_width) {
113 case 8:
114 writeb(data, mapped_reg);
115 return;
116 case 16:
117 writew(data, mapped_reg);
118 return;
119 case 32:
120 writel(data, mapped_reg);
121 return;
122 }
123
124 BUG();
125}
126
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200127u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg)
Marek Vasut3066a062017-09-15 21:13:55 +0200128{
Marek Vasut068a90b2018-06-19 06:13:42 +0200129 return sh_pfc_read_raw_reg((void __iomem *)(uintptr_t)reg, 32);
Marek Vasut3066a062017-09-15 21:13:55 +0200130}
131
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200132void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data)
Marek Vasut3066a062017-09-15 21:13:55 +0200133{
134 void __iomem *unlock_reg =
135 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
136
137 if (pfc->info->unlock_reg)
138 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
139
Marek Vasut068a90b2018-06-19 06:13:42 +0200140 sh_pfc_write_raw_reg((void __iomem *)(uintptr_t)reg, 32, data);
Marek Vasut3066a062017-09-15 21:13:55 +0200141}
142
143static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
144 const struct pinmux_cfg_reg *crp,
145 unsigned int in_pos,
146 void __iomem **mapped_regp, u32 *maskp,
147 unsigned int *posp)
148{
149 unsigned int k;
150
151 *mapped_regp = (void __iomem *)(uintptr_t)crp->reg;
152
153 if (crp->field_width) {
154 *maskp = (1 << crp->field_width) - 1;
155 *posp = crp->reg_width - ((in_pos + 1) * crp->field_width);
156 } else {
157 *maskp = (1 << crp->var_field_width[in_pos]) - 1;
158 *posp = crp->reg_width;
159 for (k = 0; k <= in_pos; k++)
160 *posp -= crp->var_field_width[k];
161 }
162}
163
164static void sh_pfc_write_config_reg(struct sh_pfc *pfc,
165 const struct pinmux_cfg_reg *crp,
166 unsigned int field, u32 value)
167{
168 void __iomem *mapped_reg;
169 void __iomem *unlock_reg =
170 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
171 unsigned int pos;
172 u32 mask, data;
173
174 sh_pfc_config_reg_helper(pfc, crp, field, &mapped_reg, &mask, &pos);
175
176 dev_dbg(pfc->dev, "write_reg addr = %x, value = 0x%x, field = %u, "
177 "r_width = %u, f_width = %u\n",
178 crp->reg, value, field, crp->reg_width, crp->field_width);
179
180 mask = ~(mask << pos);
181 value = value << pos;
182
183 data = sh_pfc_read_raw_reg(mapped_reg, crp->reg_width);
184 data &= mask;
185 data |= value;
186
187 if (pfc->info->unlock_reg)
188 sh_pfc_write_raw_reg(unlock_reg, 32, ~data);
189
190 sh_pfc_write_raw_reg(mapped_reg, crp->reg_width, data);
191}
192
193static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
194 const struct pinmux_cfg_reg **crp,
195 unsigned int *fieldp, u32 *valuep)
196{
197 unsigned int k = 0;
198
199 while (1) {
200 const struct pinmux_cfg_reg *config_reg =
201 pfc->info->cfg_regs + k;
202 unsigned int r_width = config_reg->reg_width;
203 unsigned int f_width = config_reg->field_width;
204 unsigned int curr_width;
205 unsigned int bit_pos;
206 unsigned int pos = 0;
207 unsigned int m = 0;
208
209 if (!r_width)
210 break;
211
212 for (bit_pos = 0; bit_pos < r_width; bit_pos += curr_width) {
213 u32 ncomb;
214 u32 n;
215
216 if (f_width)
217 curr_width = f_width;
218 else
219 curr_width = config_reg->var_field_width[m];
220
221 ncomb = 1 << curr_width;
222 for (n = 0; n < ncomb; n++) {
223 if (config_reg->enum_ids[pos + n] == enum_id) {
224 *crp = config_reg;
225 *fieldp = m;
226 *valuep = n;
227 return 0;
228 }
229 }
230 pos += ncomb;
231 m++;
232 }
233 k++;
234 }
235
236 return -EINVAL;
237}
238
239static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
240 u16 *enum_idp)
241{
242 const u16 *data = pfc->info->pinmux_data;
243 unsigned int k;
244
245 if (pos) {
246 *enum_idp = data[pos + 1];
247 return pos + 1;
248 }
249
250 for (k = 0; k < pfc->info->pinmux_data_size; k++) {
251 if (data[k] == mark) {
252 *enum_idp = data[k + 1];
253 return k + 1;
254 }
255 }
256
257 dev_err(pfc->dev, "cannot locate data/mark enum_id for mark %d\n",
258 mark);
259 return -EINVAL;
260}
261
262int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
263{
264 const struct pinmux_range *range;
265 int pos = 0;
266
267 switch (pinmux_type) {
268 case PINMUX_TYPE_GPIO:
269 case PINMUX_TYPE_FUNCTION:
270 range = NULL;
271 break;
272
273 case PINMUX_TYPE_OUTPUT:
274 range = &pfc->info->output;
275 break;
276
277 case PINMUX_TYPE_INPUT:
278 range = &pfc->info->input;
279 break;
280
281 default:
282 return -EINVAL;
283 }
284
285 /* Iterate over all the configuration fields we need to update. */
286 while (1) {
287 const struct pinmux_cfg_reg *cr;
288 unsigned int field;
289 u16 enum_id;
290 u32 value;
291 int in_range;
292 int ret;
293
294 pos = sh_pfc_mark_to_enum(pfc, mark, pos, &enum_id);
295 if (pos < 0)
296 return pos;
297
298 if (!enum_id)
299 break;
300
301 /* Check if the configuration field selects a function. If it
302 * doesn't, skip the field if it's not applicable to the
303 * requested pinmux type.
304 */
305 in_range = sh_pfc_enum_in_range(enum_id, &pfc->info->function);
306 if (!in_range) {
307 if (pinmux_type == PINMUX_TYPE_FUNCTION) {
308 /* Functions are allowed to modify all
309 * fields.
310 */
311 in_range = 1;
312 } else if (pinmux_type != PINMUX_TYPE_GPIO) {
313 /* Input/output types can only modify fields
314 * that correspond to their respective ranges.
315 */
316 in_range = sh_pfc_enum_in_range(enum_id, range);
317
318 /*
319 * special case pass through for fixed
320 * input-only or output-only pins without
321 * function enum register association.
322 */
323 if (in_range && enum_id == range->force)
324 continue;
325 }
326 /* GPIOs are only allowed to modify function fields. */
327 }
328
329 if (!in_range)
330 continue;
331
332 ret = sh_pfc_get_config_reg(pfc, enum_id, &cr, &field, &value);
333 if (ret < 0)
334 return ret;
335
336 sh_pfc_write_config_reg(pfc, cr, field, value);
337 }
338
339 return 0;
340}
341
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200342const struct pinmux_bias_reg *
343sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
344 unsigned int *bit)
Marek Vasut3066a062017-09-15 21:13:55 +0200345{
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200346 unsigned int i, j;
Marek Vasut3066a062017-09-15 21:13:55 +0200347
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200348 for (i = 0; pfc->info->bias_regs[i].puen; i++) {
349 for (j = 0; j < ARRAY_SIZE(pfc->info->bias_regs[i].pins); j++) {
350 if (pfc->info->bias_regs[i].pins[j] == pin) {
351 *bit = j;
352 return &pfc->info->bias_regs[i];
353 }
354 }
355 }
Marek Vasut3066a062017-09-15 21:13:55 +0200356
Marek Vasuteb13e0f2018-06-10 16:05:48 +0200357 WARN_ONCE(1, "Pin %u is not in bias info list\n", pin);
Marek Vasut3066a062017-09-15 21:13:55 +0200358
359 return NULL;
360}
361
362static int sh_pfc_init_ranges(struct sh_pfc *pfc)
363{
364 struct sh_pfc_pin_range *range;
365 unsigned int nr_ranges;
366 unsigned int i;
367
368 if (pfc->info->pins[0].pin == (u16)-1) {
369 /* Pin number -1 denotes that the SoC doesn't report pin numbers
370 * in its pin arrays yet. Consider the pin numbers range as
371 * continuous and allocate a single range.
372 */
373 pfc->nr_ranges = 1;
374 pfc->ranges = kzalloc(sizeof(*pfc->ranges), GFP_KERNEL);
375 if (pfc->ranges == NULL)
376 return -ENOMEM;
377
378 pfc->ranges->start = 0;
379 pfc->ranges->end = pfc->info->nr_pins - 1;
380 pfc->nr_gpio_pins = pfc->info->nr_pins;
381
382 return 0;
383 }
384
385 /* Count, allocate and fill the ranges. The PFC SoC data pins array must
386 * be sorted by pin numbers, and pins without a GPIO port must come
387 * last.
388 */
389 for (i = 1, nr_ranges = 1; i < pfc->info->nr_pins; ++i) {
390 if (pfc->info->pins[i-1].pin != pfc->info->pins[i].pin - 1)
391 nr_ranges++;
392 }
393
394 pfc->nr_ranges = nr_ranges;
395 pfc->ranges = kzalloc(sizeof(*pfc->ranges) * nr_ranges, GFP_KERNEL);
396 if (pfc->ranges == NULL)
397 return -ENOMEM;
398
399 range = pfc->ranges;
400 range->start = pfc->info->pins[0].pin;
401
402 for (i = 1; i < pfc->info->nr_pins; ++i) {
403 if (pfc->info->pins[i-1].pin == pfc->info->pins[i].pin - 1)
404 continue;
405
406 range->end = pfc->info->pins[i-1].pin;
407 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
408 pfc->nr_gpio_pins = range->end + 1;
409
410 range++;
411 range->start = pfc->info->pins[i].pin;
412 }
413
414 range->end = pfc->info->pins[i-1].pin;
415 if (!(pfc->info->pins[i-1].configs & SH_PFC_PIN_CFG_NO_GPIO))
416 pfc->nr_gpio_pins = range->end + 1;
417
418 return 0;
419}
420
421static int sh_pfc_pinctrl_get_pins_count(struct udevice *dev)
422{
423 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
424
425 return priv->pfc.info->nr_pins;
426}
427
428static const char *sh_pfc_pinctrl_get_pin_name(struct udevice *dev,
429 unsigned selector)
430{
431 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
432
433 return priv->pfc.info->pins[selector].name;
434}
435
436static int sh_pfc_pinctrl_get_groups_count(struct udevice *dev)
437{
438 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
439
440 return priv->pfc.info->nr_groups;
441}
442
443static const char *sh_pfc_pinctrl_get_group_name(struct udevice *dev,
444 unsigned selector)
445{
446 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
447
448 return priv->pfc.info->groups[selector].name;
449}
450
451static int sh_pfc_pinctrl_get_functions_count(struct udevice *dev)
452{
453 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
454
455 return priv->pfc.info->nr_functions;
456}
457
458static const char *sh_pfc_pinctrl_get_function_name(struct udevice *dev,
459 unsigned selector)
460{
461 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
462
463 return priv->pfc.info->functions[selector].name;
464}
465
Marek Vasut02d34f02019-04-21 22:46:25 +0200466static int sh_pfc_gpio_request_enable(struct udevice *dev,
467 unsigned pin_selector)
Marek Vasut489d79c2017-11-26 18:07:29 +0100468{
469 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
470 struct sh_pfc_pinctrl *pmx = &priv->pmx;
471 struct sh_pfc *pfc = &priv->pfc;
472 struct sh_pfc_pin_config *cfg;
473 const struct sh_pfc_pin *pin = NULL;
Marek Vasut0cc19362019-04-21 22:46:25 +0200474 int i, ret, idx;
Marek Vasut489d79c2017-11-26 18:07:29 +0100475
titron09bf4982019-07-22 17:45:37 +0800476 for (i = 0; i < pfc->info->nr_pins; i++) {
Marek Vasut489d79c2017-11-26 18:07:29 +0100477 if (priv->pfc.info->pins[i].pin != pin_selector)
478 continue;
479
480 pin = &priv->pfc.info->pins[i];
481 break;
482 }
483
484 if (!pin)
485 return -EINVAL;
486
487 idx = sh_pfc_get_pin_index(pfc, pin->pin);
488 cfg = &pmx->configs[idx];
489
490 if (cfg->type != PINMUX_TYPE_NONE)
491 return -EBUSY;
492
Marek Vasut0cc19362019-04-21 22:46:25 +0200493 ret = sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_GPIO);
494 if (ret)
495 return ret;
496
497 cfg->type = PINMUX_TYPE_GPIO;
498
499 return 0;
Marek Vasut489d79c2017-11-26 18:07:29 +0100500}
501
Marek Vasut02d34f02019-04-21 22:46:25 +0200502static int sh_pfc_gpio_disable_free(struct udevice *dev,
503 unsigned pin_selector)
504{
505 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
506 struct sh_pfc_pinctrl *pmx = &priv->pmx;
507 struct sh_pfc *pfc = &priv->pfc;
508 struct sh_pfc_pin_config *cfg;
509 const struct sh_pfc_pin *pin = NULL;
510 int i, idx;
511
titron09bf4982019-07-22 17:45:37 +0800512 for (i = 0; i < pfc->info->nr_pins; i++) {
Marek Vasut02d34f02019-04-21 22:46:25 +0200513 if (priv->pfc.info->pins[i].pin != pin_selector)
514 continue;
515
516 pin = &priv->pfc.info->pins[i];
517 break;
518 }
519
520 if (!pin)
521 return -EINVAL;
522
523 idx = sh_pfc_get_pin_index(pfc, pin->pin);
524 cfg = &pmx->configs[idx];
525
526 cfg->type = PINMUX_TYPE_NONE;
527
528 return 0;
529}
530
Marek Vasut5e6db842017-11-26 17:42:16 +0100531static int sh_pfc_pinctrl_pin_set(struct udevice *dev, unsigned pin_selector,
532 unsigned func_selector)
533{
534 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
535 struct sh_pfc_pinctrl *pmx = &priv->pmx;
536 struct sh_pfc *pfc = &priv->pfc;
537 const struct sh_pfc_pin *pin = &priv->pfc.info->pins[pin_selector];
538 int idx = sh_pfc_get_pin_index(pfc, pin->pin);
539 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
540
541 if (cfg->type != PINMUX_TYPE_NONE)
542 return -EBUSY;
543
544 return sh_pfc_config_mux(pfc, pin->enum_id, PINMUX_TYPE_FUNCTION);
545}
546
Marek Vasut3066a062017-09-15 21:13:55 +0200547static int sh_pfc_pinctrl_group_set(struct udevice *dev, unsigned group_selector,
548 unsigned func_selector)
549{
550 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
551 struct sh_pfc_pinctrl *pmx = &priv->pmx;
552 struct sh_pfc *pfc = &priv->pfc;
553 const struct sh_pfc_pin_group *grp = &priv->pfc.info->groups[group_selector];
554 unsigned int i;
555 int ret = 0;
556
557 for (i = 0; i < grp->nr_pins; ++i) {
558 int idx = sh_pfc_get_pin_index(pfc, grp->pins[i]);
559 struct sh_pfc_pin_config *cfg = &pmx->configs[idx];
560
561 if (cfg->type != PINMUX_TYPE_NONE) {
562 ret = -EBUSY;
563 goto done;
564 }
565 }
566
567 for (i = 0; i < grp->nr_pins; ++i) {
568 ret = sh_pfc_config_mux(pfc, grp->mux[i], PINMUX_TYPE_FUNCTION);
569 if (ret < 0)
570 break;
571 }
572
573done:
574 return ret;
575}
Marek Vasutc9dd9ae2017-09-28 00:56:24 +0200576#if CONFIG_IS_ENABLED(PINCONF)
577static const struct pinconf_param sh_pfc_pinconf_params[] = {
578 { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
579 { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
580 { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
581 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
582 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 },
583};
584
585static void __iomem *
586sh_pfc_pinconf_find_drive_strength_reg(struct sh_pfc *pfc, unsigned int pin,
587 unsigned int *offset, unsigned int *size)
588{
589 const struct pinmux_drive_reg_field *field;
590 const struct pinmux_drive_reg *reg;
591 unsigned int i;
592
593 for (reg = pfc->info->drive_regs; reg->reg; ++reg) {
594 for (i = 0; i < ARRAY_SIZE(reg->fields); ++i) {
595 field = &reg->fields[i];
596
597 if (field->size && field->pin == pin) {
598 *offset = field->offset;
599 *size = field->size;
600
601 return (void __iomem *)(uintptr_t)reg->reg;
602 }
603 }
604 }
605
606 return NULL;
607}
608
609static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
610 unsigned int pin, u16 strength)
611{
612 unsigned int offset;
613 unsigned int size;
614 unsigned int step;
615 void __iomem *reg;
616 void __iomem *unlock_reg =
617 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
618 u32 val;
619
620 reg = sh_pfc_pinconf_find_drive_strength_reg(pfc, pin, &offset, &size);
621 if (!reg)
622 return -EINVAL;
623
624 step = size == 2 ? 6 : 3;
625
626 if (strength < step || strength > 24)
627 return -EINVAL;
628
629 /* Convert the value from mA based on a full drive strength value of
630 * 24mA. We can make the full value configurable later if needed.
631 */
632 strength = strength / step - 1;
633
634 val = sh_pfc_read_raw_reg(reg, 32);
Marek Vasut0d9c8102018-06-13 08:02:55 +0200635 val &= ~GENMASK(offset + 4 - 1, offset);
Marek Vasutc9dd9ae2017-09-28 00:56:24 +0200636 val |= strength << offset;
637
638 if (unlock_reg)
639 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
640
641 sh_pfc_write_raw_reg(reg, 32, val);
642
643 return 0;
644}
645
646/* Check whether the requested parameter is supported for a pin. */
647static bool sh_pfc_pinconf_validate(struct sh_pfc *pfc, unsigned int _pin,
648 unsigned int param)
649{
650 int idx = sh_pfc_get_pin_index(pfc, _pin);
651 const struct sh_pfc_pin *pin = &pfc->info->pins[idx];
652
653 switch (param) {
654 case PIN_CONFIG_BIAS_DISABLE:
655 return pin->configs &
656 (SH_PFC_PIN_CFG_PULL_UP | SH_PFC_PIN_CFG_PULL_DOWN);
657
658 case PIN_CONFIG_BIAS_PULL_UP:
659 return pin->configs & SH_PFC_PIN_CFG_PULL_UP;
660
661 case PIN_CONFIG_BIAS_PULL_DOWN:
662 return pin->configs & SH_PFC_PIN_CFG_PULL_DOWN;
663
664 case PIN_CONFIG_DRIVE_STRENGTH:
665 return pin->configs & SH_PFC_PIN_CFG_DRIVE_STRENGTH;
666
667 case PIN_CONFIG_POWER_SOURCE:
668 return pin->configs & SH_PFC_PIN_CFG_IO_VOLTAGE;
669
670 default:
671 return false;
672 }
673}
674
675static int sh_pfc_pinconf_set(struct sh_pfc_pinctrl *pmx, unsigned _pin,
676 unsigned int param, unsigned int arg)
677{
678 struct sh_pfc *pfc = pmx->pfc;
679 void __iomem *pocctrl;
680 void __iomem *unlock_reg =
681 (void __iomem *)(uintptr_t)pfc->info->unlock_reg;
682 u32 addr, val;
683 int bit, ret;
684
685 if (!sh_pfc_pinconf_validate(pfc, _pin, param))
686 return -ENOTSUPP;
687
688 switch (param) {
689 case PIN_CONFIG_BIAS_PULL_UP:
690 case PIN_CONFIG_BIAS_PULL_DOWN:
691 case PIN_CONFIG_BIAS_DISABLE:
692 if (!pfc->info->ops || !pfc->info->ops->set_bias)
693 return -ENOTSUPP;
694
695 pfc->info->ops->set_bias(pfc, _pin, param);
696
697 break;
698
699 case PIN_CONFIG_DRIVE_STRENGTH:
700 ret = sh_pfc_pinconf_set_drive_strength(pfc, _pin, arg);
701 if (ret < 0)
702 return ret;
703
704 break;
705
706 case PIN_CONFIG_POWER_SOURCE:
707 if (!pfc->info->ops || !pfc->info->ops->pin_to_pocctrl)
708 return -ENOTSUPP;
709
710 bit = pfc->info->ops->pin_to_pocctrl(pfc, _pin, &addr);
711 if (bit < 0) {
712 printf("invalid pin %#x", _pin);
713 return bit;
714 }
715
716 if (arg != 1800 && arg != 3300)
717 return -EINVAL;
718
719 pocctrl = (void __iomem *)(uintptr_t)addr;
720
721 val = sh_pfc_read_raw_reg(pocctrl, 32);
722 if (arg == 3300)
723 val |= BIT(bit);
724 else
725 val &= ~BIT(bit);
726
727 if (unlock_reg)
728 sh_pfc_write_raw_reg(unlock_reg, 32, ~val);
729
730 sh_pfc_write_raw_reg(pocctrl, 32, val);
731
732 break;
733
734 default:
735 return -ENOTSUPP;
736 }
737
738 return 0;
739}
740
Marek Vasut5e6db842017-11-26 17:42:16 +0100741static int sh_pfc_pinconf_pin_set(struct udevice *dev,
742 unsigned int pin_selector,
743 unsigned int param, unsigned int arg)
744{
745 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
746 struct sh_pfc_pinctrl *pmx = &priv->pmx;
747 struct sh_pfc *pfc = &priv->pfc;
748 const struct sh_pfc_pin *pin = &pfc->info->pins[pin_selector];
749
750 sh_pfc_pinconf_set(pmx, pin->pin, param, arg);
751
752 return 0;
753}
Marek Vasutc9dd9ae2017-09-28 00:56:24 +0200754
755static int sh_pfc_pinconf_group_set(struct udevice *dev,
756 unsigned int group_selector,
757 unsigned int param, unsigned int arg)
758{
759 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
760 struct sh_pfc_pinctrl *pmx = &priv->pmx;
761 struct sh_pfc *pfc = &priv->pfc;
762 const struct sh_pfc_pin_group *grp = &pfc->info->groups[group_selector];
763 unsigned int i;
764
765 for (i = 0; i < grp->nr_pins; i++)
766 sh_pfc_pinconf_set(pmx, grp->pins[i], param, arg);
767
768 return 0;
769}
770#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200771
772static struct pinctrl_ops sh_pfc_pinctrl_ops = {
773 .get_pins_count = sh_pfc_pinctrl_get_pins_count,
774 .get_pin_name = sh_pfc_pinctrl_get_pin_name,
775 .get_groups_count = sh_pfc_pinctrl_get_groups_count,
776 .get_group_name = sh_pfc_pinctrl_get_group_name,
777 .get_functions_count = sh_pfc_pinctrl_get_functions_count,
778 .get_function_name = sh_pfc_pinctrl_get_function_name,
779
Marek Vasutc9dd9ae2017-09-28 00:56:24 +0200780#if CONFIG_IS_ENABLED(PINCONF)
781 .pinconf_num_params = ARRAY_SIZE(sh_pfc_pinconf_params),
782 .pinconf_params = sh_pfc_pinconf_params,
Marek Vasut5e6db842017-11-26 17:42:16 +0100783 .pinconf_set = sh_pfc_pinconf_pin_set,
Marek Vasutc9dd9ae2017-09-28 00:56:24 +0200784 .pinconf_group_set = sh_pfc_pinconf_group_set,
785#endif
Marek Vasut5e6db842017-11-26 17:42:16 +0100786 .pinmux_set = sh_pfc_pinctrl_pin_set,
Marek Vasut3066a062017-09-15 21:13:55 +0200787 .pinmux_group_set = sh_pfc_pinctrl_group_set,
788 .set_state = pinctrl_generic_set_state,
Marek Vasut02d34f02019-04-21 22:46:25 +0200789
790 .gpio_request_enable = sh_pfc_gpio_request_enable,
791 .gpio_disable_free = sh_pfc_gpio_disable_free,
Marek Vasut3066a062017-09-15 21:13:55 +0200792};
793
794static int sh_pfc_map_pins(struct sh_pfc *pfc, struct sh_pfc_pinctrl *pmx)
795{
796 unsigned int i;
797
798 /* Allocate and initialize the pins and configs arrays. */
799 pmx->configs = kzalloc(sizeof(*pmx->configs) * pfc->info->nr_pins,
800 GFP_KERNEL);
801 if (unlikely(!pmx->configs))
802 return -ENOMEM;
803
804 for (i = 0; i < pfc->info->nr_pins; ++i) {
805 struct sh_pfc_pin_config *cfg = &pmx->configs[i];
806 cfg->type = PINMUX_TYPE_NONE;
807 }
808
809 return 0;
810}
811
812
813static int sh_pfc_pinctrl_probe(struct udevice *dev)
814{
815 struct sh_pfc_pinctrl_priv *priv = dev_get_priv(dev);
816 enum sh_pfc_model model = dev_get_driver_data(dev);
817 fdt_addr_t base;
818
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +0900819 base = dev_read_addr(dev);
Marek Vasut3066a062017-09-15 21:13:55 +0200820 if (base == FDT_ADDR_T_NONE)
821 return -EINVAL;
822
823 priv->pfc.regs = devm_ioremap(dev, base, SZ_2K);
824 if (!priv->pfc.regs)
825 return -ENOMEM;
826
Marek Vasutc40f2d62018-01-17 22:18:59 +0100827#ifdef CONFIG_PINCTRL_PFC_R8A7790
828 if (model == SH_PFC_R8A7790)
829 priv->pfc.info = &r8a7790_pinmux_info;
830#endif
Marek Vasut06ef9e82018-01-17 17:14:45 +0100831#ifdef CONFIG_PINCTRL_PFC_R8A7791
832 if (model == SH_PFC_R8A7791)
833 priv->pfc.info = &r8a7791_pinmux_info;
834#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100835#ifdef CONFIG_PINCTRL_PFC_R8A7792
836 if (model == SH_PFC_R8A7792)
837 priv->pfc.info = &r8a7792_pinmux_info;
838#endif
Marek Vasut06ef9e82018-01-17 17:14:45 +0100839#ifdef CONFIG_PINCTRL_PFC_R8A7793
840 if (model == SH_PFC_R8A7793)
841 priv->pfc.info = &r8a7793_pinmux_info;
842#endif
Marek Vasut4dd88d52018-01-17 22:33:59 +0100843#ifdef CONFIG_PINCTRL_PFC_R8A7794
844 if (model == SH_PFC_R8A7794)
845 priv->pfc.info = &r8a7794_pinmux_info;
846#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200847#ifdef CONFIG_PINCTRL_PFC_R8A7795
848 if (model == SH_PFC_R8A7795)
849 priv->pfc.info = &r8a7795_pinmux_info;
850#endif
851#ifdef CONFIG_PINCTRL_PFC_R8A7796
852 if (model == SH_PFC_R8A7796)
853 priv->pfc.info = &r8a7796_pinmux_info;
854#endif
Adam Ford96980fb2020-06-30 09:30:09 -0500855#ifdef CONFIG_PINCTRL_PFC_R8A774A1
856 if (model == SH_PFC_R8A774A1)
857 priv->pfc.info = &r8a774a1_pinmux_info;
858#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000859#ifdef CONFIG_PINCTRL_PFC_R8A774B1
860 if (model == SH_PFC_R8A774B1)
861 priv->pfc.info = &r8a774b1_pinmux_info;
862#endif
Biju Das121bd002020-10-28 10:34:22 +0000863#ifdef CONFIG_PINCTRL_PFC_R8A774E1
864 if (model == SH_PFC_R8A774E1)
865 priv->pfc.info = &r8a774e1_pinmux_info;
866#endif
Marek Vasut72269e02019-03-04 01:32:44 +0100867#ifdef CONFIG_PINCTRL_PFC_R8A77965
868 if (model == SH_PFC_R8A77965)
869 priv->pfc.info = &r8a77965_pinmux_info;
870#endif
Marek Vasuta0e11e52017-10-09 20:57:29 +0200871#ifdef CONFIG_PINCTRL_PFC_R8A77970
872 if (model == SH_PFC_R8A77970)
873 priv->pfc.info = &r8a77970_pinmux_info;
874#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200875#ifdef CONFIG_PINCTRL_PFC_R8A77980
876 if (model == SH_PFC_R8A77980)
877 priv->pfc.info = &r8a77980_pinmux_info;
878#endif
Marek Vasut68a77042018-04-26 13:09:20 +0200879#ifdef CONFIG_PINCTRL_PFC_R8A77990
880 if (model == SH_PFC_R8A77990)
881 priv->pfc.info = &r8a77990_pinmux_info;
882#endif
Marek Vasut7d35e642017-10-08 20:57:37 +0200883#ifdef CONFIG_PINCTRL_PFC_R8A77995
884 if (model == SH_PFC_R8A77995)
885 priv->pfc.info = &r8a77995_pinmux_info;
886#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200887
888 priv->pmx.pfc = &priv->pfc;
889 sh_pfc_init_ranges(&priv->pfc);
890 sh_pfc_map_pins(&priv->pfc, &priv->pmx);
891
892 return 0;
893}
894
895static const struct udevice_id sh_pfc_pinctrl_ids[] = {
Marek Vasutc40f2d62018-01-17 22:18:59 +0100896#ifdef CONFIG_PINCTRL_PFC_R8A7790
897 {
898 .compatible = "renesas,pfc-r8a7790",
899 .data = SH_PFC_R8A7790,
900 },
901#endif
Marek Vasut06ef9e82018-01-17 17:14:45 +0100902#ifdef CONFIG_PINCTRL_PFC_R8A7791
903 {
904 .compatible = "renesas,pfc-r8a7791",
905 .data = SH_PFC_R8A7791,
906 },
907#endif
Marek Vasut1ef39302018-01-17 22:29:50 +0100908#ifdef CONFIG_PINCTRL_PFC_R8A7792
909 {
910 .compatible = "renesas,pfc-r8a7792",
911 .data = SH_PFC_R8A7792,
912 },
913#endif
Marek Vasut06ef9e82018-01-17 17:14:45 +0100914#ifdef CONFIG_PINCTRL_PFC_R8A7793
915 {
916 .compatible = "renesas,pfc-r8a7793",
917 .data = SH_PFC_R8A7793,
918 },
919#endif
Marek Vasut4dd88d52018-01-17 22:33:59 +0100920#ifdef CONFIG_PINCTRL_PFC_R8A7794
921 {
922 .compatible = "renesas,pfc-r8a7794",
923 .data = SH_PFC_R8A7794,
924 },
925#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200926#ifdef CONFIG_PINCTRL_PFC_R8A7795
927 {
928 .compatible = "renesas,pfc-r8a7795",
929 .data = SH_PFC_R8A7795,
930 },
931#endif
932#ifdef CONFIG_PINCTRL_PFC_R8A7796
933 {
934 .compatible = "renesas,pfc-r8a7796",
935 .data = SH_PFC_R8A7796,
Marek Vasut72269e02019-03-04 01:32:44 +0100936 },
937#endif
Adam Ford96980fb2020-06-30 09:30:09 -0500938#ifdef CONFIG_PINCTRL_PFC_R8A774A1
939 {
940 .compatible = "renesas,pfc-r8a774a1",
941 .data = SH_PFC_R8A774A1,
942 },
943#endif
Biju Dasd1d78882020-10-28 10:34:21 +0000944#ifdef CONFIG_PINCTRL_PFC_R8A774B1
945 {
946 .compatible = "renesas,pfc-r8a774b1",
947 .data = SH_PFC_R8A774B1,
948 },
949#endif
Biju Das121bd002020-10-28 10:34:22 +0000950#ifdef CONFIG_PINCTRL_PFC_R8A774E1
951 {
952 .compatible = "renesas,pfc-r8a774e1",
953 .data = SH_PFC_R8A774E1,
954 },
955#endif
Marek Vasut72269e02019-03-04 01:32:44 +0100956#ifdef CONFIG_PINCTRL_PFC_R8A77965
957 {
Marek Vasut20d721e2018-02-26 10:35:15 +0100958 .compatible = "renesas,pfc-r8a77965",
Marek Vasut72269e02019-03-04 01:32:44 +0100959 .data = SH_PFC_R8A77965,
Marek Vasut3066a062017-09-15 21:13:55 +0200960 },
961#endif
Marek Vasuta0e11e52017-10-09 20:57:29 +0200962#ifdef CONFIG_PINCTRL_PFC_R8A77970
963 {
964 .compatible = "renesas,pfc-r8a77970",
965 .data = SH_PFC_R8A77970,
966 },
967#endif
Marek Vasuta6a7f482019-07-29 19:59:44 +0200968#ifdef CONFIG_PINCTRL_PFC_R8A77980
969 {
970 .compatible = "renesas,pfc-r8a77980",
971 .data = SH_PFC_R8A77980,
972 },
973#endif
Marek Vasut68a77042018-04-26 13:09:20 +0200974#ifdef CONFIG_PINCTRL_PFC_R8A77990
975 {
976 .compatible = "renesas,pfc-r8a77990",
977 .data = SH_PFC_R8A77990,
978 },
979#endif
Marek Vasut7d35e642017-10-08 20:57:37 +0200980#ifdef CONFIG_PINCTRL_PFC_R8A77995
981 {
982 .compatible = "renesas,pfc-r8a77995",
983 .data = SH_PFC_R8A77995,
984 },
985#endif
Marek Vasut3066a062017-09-15 21:13:55 +0200986 { },
987};
988
989U_BOOT_DRIVER(pinctrl_sh_pfc) = {
990 .name = "sh_pfc_pinctrl",
991 .id = UCLASS_PINCTRL,
992 .of_match = sh_pfc_pinctrl_ids,
Simon Glass8a2b47f2020-12-03 16:55:17 -0700993 .priv_auto = sizeof(struct sh_pfc_pinctrl_priv),
Marek Vasut3066a062017-09-15 21:13:55 +0200994 .ops = &sh_pfc_pinctrl_ops,
995 .probe = sh_pfc_pinctrl_probe,
996};