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Matwey V. Kornilove768cfc2019-08-02 10:39:58 +03001// SPDX-License-Identifier: GPL-2.0+
2/*
Kever Yange68e10b2019-08-15 11:40:56 +08003 * (C) Copyright 2016-2019 Rockchip Electronics Co., Ltd
Matwey V. Kornilove768cfc2019-08-02 10:39:58 +03004 */
5
Kever Yange68e10b2019-08-15 11:40:56 +08006#include "rk3328-u-boot.dtsi"
Kever Yange0d3f882019-08-02 10:40:00 +03007#include "rk3328-sdram-ddr3-666.dtsi"
8
Chen-Yu Tsaie7184852020-04-27 14:52:46 +08009/{
Chen-Yu Tsai8cd428d2020-04-27 14:52:47 +080010 gmac_clkin: external-gmac-clock {
11 compatible = "fixed-clock";
12 clock-frequency = <125000000>;
13 clock-output-names = "gmac_clkin";
14 #clock-cells = <0>;
15 };
16
Chen-Yu Tsaie7184852020-04-27 14:52:46 +080017 vcc5v0_host_xhci: vcc5v0-host-xhci-drv {
18 compatible = "regulator-fixed";
19 enable-active-high;
20 gpio = <&gpio0 0 GPIO_ACTIVE_HIGH>;
21 regulator-name = "vcc5v0_host_xhci";
22 regulator-min-microvolt = <5000000>;
23 regulator-max-microvolt = <5000000>;
24 };
25};
26
Chen-Yu Tsai8cd428d2020-04-27 14:52:47 +080027&gmac2io {
28 phy-supply = <&vcc_phy>;
29 phy-mode = "rgmii";
30 clock_in_out = "input";
31 snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
32 snps,reset-active-low;
33 snps,reset-delays-us = <0 10000 50000>;
34 assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
35 assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>;
36 pinctrl-names = "default";
37 pinctrl-0 = <&rgmiim1_pins>;
38 tx_delay = <0x26>;
39 rx_delay = <0x11>;
40 status = "okay";
41};
42
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080043&gmac2phy {
Michal Simek50fa1182023-05-17 09:17:16 +020044 /* Integrated PHY unsupported by U-Boot */
Chen-Yu Tsaib67079b2020-04-27 14:52:52 +080045 status = "broken";
46};
Jonas Karlmand6a1b572024-02-17 00:22:34 +000047
48&vcc_sd {
49 bootph-pre-ram;
50};