blob: 00e9c44fdf377e7893537278fe2bf43aa070f1d0 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +00002/*
3 * Embest/Timll DevKit3250 board configuration file
4 *
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +03005 * Copyright (C) 2011-2015 Vladimir Zapolskiy <vz@mleia.com>
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +00006 */
7
8#ifndef __CONFIG_DEVKIT3250_H__
9#define __CONFIG_DEVKIT3250_H__
10
11/* SoC and board defines */
Alexey Brodkin267d8e22014-02-26 17:47:58 +040012#include <linux/sizes.h>
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000013#include <asm/arch/cpu.h>
14
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000015#define CONFIG_MACH_TYPE MACH_TYPE_DEVKIT3250
16
17#define CONFIG_SYS_ICACHE_OFF
18#define CONFIG_SYS_DCACHE_OFF
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +030019#if !defined(CONFIG_SPL_BUILD)
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000020#define CONFIG_SKIP_LOWLEVEL_INIT
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +030021#endif
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000022
23/*
24 * Memory configurations
25 */
26#define CONFIG_NR_DRAM_BANKS 1
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000027#define CONFIG_SYS_MALLOC_LEN SZ_1M
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000028#define CONFIG_SYS_SDRAM_BASE EMC_DYCS0_BASE
29#define CONFIG_SYS_SDRAM_SIZE SZ_64M
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000030#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + SZ_32K)
31#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - SZ_1M)
32
33#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_32K)
34
35#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + SZ_4K \
36 - GENERATED_GBL_DATA_SIZE)
37
38/*
39 * Serial Driver
40 */
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030041#define CONFIG_SYS_LPC32XX_UART 5 /* UART5 */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000042
43/*
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +020044 * DMA
45 */
46#if !defined(CONFIG_SPL_BUILD)
47#define CONFIG_DMA_LPC32XX
48#endif
49
50/*
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030051 * I2C
52 */
53#define CONFIG_SYS_I2C
54#define CONFIG_SYS_I2C_LPC32XX
55#define CONFIG_SYS_I2C_SPEED 100000
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030056
57/*
58 * GPIO
59 */
60#define CONFIG_LPC32XX_GPIO
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030061
62/*
63 * SSP/SPI
64 */
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030065#define CONFIG_LPC32XX_SSP_TIMEOUT 100000
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030066
67/*
68 * Ethernet
69 */
70#define CONFIG_RMII
71#define CONFIG_PHY_SMSC
72#define CONFIG_LPC32XX_ETH
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030073#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030074
75/*
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000076 * NOR Flash
77 */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +000078#define CONFIG_SYS_MAX_FLASH_BANKS 1
79#define CONFIG_SYS_MAX_FLASH_SECT 71
80#define CONFIG_SYS_FLASH_BASE EMC_CS0_BASE
81#define CONFIG_SYS_FLASH_SIZE SZ_4M
82#define CONFIG_SYS_FLASH_CFI
83
84/*
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030085 * NAND controller
86 */
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +030087#define CONFIG_SYS_NAND_BASE SLC_NAND_BASE
88#define CONFIG_SYS_MAX_NAND_DEVICE 1
89#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
90
91/*
92 * NAND chip timings
93 */
94#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
95#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
96#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
97#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000
98#define CONFIG_LPC32XX_NAND_SLC_RDR_CLKS 14
99#define CONFIG_LPC32XX_NAND_SLC_RWIDTH 66666666
100#define CONFIG_LPC32XX_NAND_SLC_RHOLD 200000000
101#define CONFIG_LPC32XX_NAND_SLC_RSETUP 50000000
102
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300103#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
104#define CONFIG_SYS_NAND_PAGE_SIZE NAND_LARGE_BLOCK_PAGE_SIZE
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +0300105#define CONFIG_SYS_NAND_USE_FLASH_BBT
Vladimir Zapolskiya6e30ef2015-08-11 19:57:09 +0300106
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +0300107/*
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +0200108 * USB
109 */
110#define CONFIG_USB_OHCI_LPC32XX
111#define CONFIG_USB_ISP1301_I2C_ADDR 0x2d
Vladimir Zapolskiy936c2002015-12-19 23:41:23 +0200112
113/*
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000114 * U-Boot General Configurations
115 */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000116#define CONFIG_SYS_CBSIZE 1024
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000117#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
118
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +0300119/*
120 * Pass open firmware flat tree
121 */
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +0300122
123/*
124 * Environment
125 */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000126#define CONFIG_ENV_SIZE SZ_128K
Vladimir Zapolskiy3704e432015-07-18 01:47:10 +0300127#define CONFIG_ENV_OFFSET 0x000A0000
128
129#define CONFIG_BOOTCOMMAND \
130 "dhcp; " \
131 "tftp ${loadaddr} ${serverip}:${tftpdir}/${bootfile}; " \
132 "tftp ${dtbaddr} ${serverip}:${tftpdir}/devkit3250.dtb; " \
133 "setenv nfsargs ip=dhcp root=/dev/nfs nfsroot=${serverip}:${nfsroot},tcp; " \
134 "setenv bootargs ${bootargs} ${nfsargs} ${userargs}; " \
135 "bootm ${loadaddr} - ${dtbaddr}"
136
137#define CONFIG_EXTRA_ENV_SETTINGS \
138 "autoload=no\0" \
139 "ethaddr=00:01:90:00:C0:81\0" \
140 "dtbaddr=0x81000000\0" \
141 "nfsroot=/opt/projects/images/vladimir/oe/devkit3250/rootfs\0" \
142 "tftpdir=vladimir/oe/devkit3250\0" \
143 "userargs=oops=panic\0"
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000144
145/*
146 * U-Boot Commands
147 */
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000148
149/*
150 * Boot Linux
151 */
152#define CONFIG_CMDLINE_TAG
153#define CONFIG_SETUP_MEMORY_TAGS
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000154
155#define CONFIG_BOOTFILE "uImage"
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000156#define CONFIG_LOADADDR 0x80008000
157
158/*
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +0300159 * SPL specific defines
160 */
161/* SPL will be executed at offset 0 */
162#define CONFIG_SPL_TEXT_BASE 0x00000000
163
164/* SPL will use SRAM as stack */
165#define CONFIG_SPL_STACK 0x0000FFF8
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +0300166
167/* Use the framework and generic lib */
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +0300168
169/* SPL will use serial */
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +0300170
171/* SPL loads an image from NAND */
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +0300172#define CONFIG_SPL_NAND_RAW_ONLY
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +0300173#define CONFIG_SPL_NAND_DRIVERS
174
Vladimir Zapolskiy89f86a22015-07-18 01:47:11 +0300175#define CONFIG_SPL_NAND_ECC
176#define CONFIG_SPL_NAND_SOFTECC
177
178#define CONFIG_SPL_MAX_SIZE 0x20000
179#define CONFIG_SPL_PAD_TO CONFIG_SPL_MAX_SIZE
180
181/* U-Boot will be 0x60000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */
182#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
183#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x60000
184
185#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
186#define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
187
188/* See common/spl/spl.c spl_set_header_raw_uboot() */
189#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
190
191/*
Vladimir Zapolskiy3ed0fcf2012-04-19 04:33:10 +0000192 * Include SoC specific configuration
193 */
194#include <asm/arch/config.h>
195
196#endif /* __CONFIG_DEVKIT3250_H__*/