| Alexandre Vicenzi | bc592bd | 2021-03-26 13:37:10 +0100 | [diff] [blame] | 1 | CONFIG_ARM=y |
| Tom Rini | e1e8544 | 2021-08-27 21:18:30 -0400 | [diff] [blame] | 2 | CONFIG_SKIP_LOWLEVEL_INIT=y |
| Peng Fan | c8a61c0 | 2022-04-13 17:47:20 +0800 | [diff] [blame] | 3 | CONFIG_COUNTER_FREQUENCY=24000000 |
| Alexandre Vicenzi | bc592bd | 2021-03-26 13:37:10 +0100 | [diff] [blame] | 4 | CONFIG_ARCH_ROCKCHIP=y |
| 5 | CONFIG_SYS_TEXT_BASE=0x00200000 |
| 6 | CONFIG_NR_DRAM_BANKS=1 |
| 7 | CONFIG_ENV_OFFSET=0x3F8000 |
| Tom Rini | a20e51f | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 8 | CONFIG_DEFAULT_DEVICE_TREE="rk3399-nanopi-m4b" |
| Alexandre Vicenzi | bc592bd | 2021-03-26 13:37:10 +0100 | [diff] [blame] | 9 | CONFIG_ROCKCHIP_RK3399=y |
| 10 | CONFIG_TARGET_EVB_RK3399=y |
| 11 | CONFIG_DEBUG_UART_BASE=0xFF1A0000 |
| 12 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| Tom Rini | 0997ee0 | 2021-08-23 10:25:31 -0400 | [diff] [blame] | 13 | CONFIG_SYS_LOAD_ADDR=0x800800 |
| Tom Rini | 4b2fcb3 | 2022-04-08 13:36:51 -0400 | [diff] [blame] | 14 | CONFIG_DEBUG_UART=y |
| Tom Rini | 4ddbade | 2022-05-25 12:16:03 -0400 | [diff] [blame] | 15 | CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y |
| 16 | CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x300000 |
| Alexandre Vicenzi | bc592bd | 2021-03-26 13:37:10 +0100 | [diff] [blame] | 17 | CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-nanopi-m4b.dtb" |
| 18 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| Tom Rini | abb0f52 | 2022-05-16 17:20:26 -0400 | [diff] [blame] | 19 | CONFIG_SPL_MAX_SIZE=0x2e000 |
| 20 | CONFIG_SPL_PAD_TO=0x7f8000 |
| Tom Rini | 0cb89e7 | 2022-05-19 15:09:22 -0400 | [diff] [blame] | 21 | CONFIG_SPL_BSS_MAX_SIZE=0x2000 |
| Alexandre Vicenzi | bc592bd | 2021-03-26 13:37:10 +0100 | [diff] [blame] | 22 | # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set |
| Tom Rini | 8a14ac4 | 2022-05-26 13:13:21 -0400 | [diff] [blame^] | 23 | # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set |
| 24 | CONFIG_SPL_STACK=0x400000 |
| Alexandre Vicenzi | bc592bd | 2021-03-26 13:37:10 +0100 | [diff] [blame] | 25 | CONFIG_SPL_STACK_R=y |
| 26 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x10000 |
| 27 | CONFIG_TPL=y |
| 28 | CONFIG_CMD_BOOTZ=y |
| 29 | CONFIG_CMD_GPT=y |
| 30 | CONFIG_CMD_MMC=y |
| 31 | CONFIG_CMD_USB=y |
| 32 | # CONFIG_CMD_SETEXPR is not set |
| 33 | CONFIG_CMD_TIME=y |
| 34 | CONFIG_SPL_OF_CONTROL=y |
| 35 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 36 | CONFIG_ENV_IS_IN_MMC=y |
| 37 | CONFIG_SYS_RELOC_GD_ENV_ADDR=y |
| 38 | CONFIG_ROCKCHIP_GPIO=y |
| 39 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 40 | CONFIG_MMC_DW=y |
| 41 | CONFIG_MMC_DW_ROCKCHIP=y |
| 42 | CONFIG_MMC_SDHCI=y |
| 43 | CONFIG_MMC_SDHCI_ROCKCHIP=y |
| 44 | CONFIG_DM_ETH=y |
| 45 | CONFIG_ETH_DESIGNWARE=y |
| 46 | CONFIG_GMAC_ROCKCHIP=y |
| 47 | CONFIG_PMIC_RK8XX=y |
| 48 | CONFIG_REGULATOR_PWM=y |
| 49 | CONFIG_REGULATOR_RK8XX=y |
| 50 | CONFIG_PWM_ROCKCHIP=y |
| 51 | CONFIG_BAUDRATE=1500000 |
| 52 | CONFIG_DEBUG_UART_SHIFT=2 |
| 53 | CONFIG_SYSRESET=y |
| 54 | CONFIG_USB=y |
| 55 | CONFIG_USB_XHCI_HCD=y |
| 56 | CONFIG_USB_XHCI_DWC3=y |
| 57 | CONFIG_USB_EHCI_HCD=y |
| 58 | CONFIG_USB_EHCI_GENERIC=y |
| 59 | CONFIG_USB_KEYBOARD=y |
| 60 | CONFIG_USB_HOST_ETHER=y |
| 61 | CONFIG_USB_ETHER_ASIX=y |
| 62 | CONFIG_USB_ETHER_ASIX88179=y |
| 63 | CONFIG_USB_ETHER_MCS7830=y |
| 64 | CONFIG_USB_ETHER_RTL8152=y |
| 65 | CONFIG_USB_ETHER_SMSC95XX=y |
| 66 | CONFIG_DM_VIDEO=y |
| 67 | CONFIG_DISPLAY=y |
| 68 | CONFIG_VIDEO_ROCKCHIP=y |
| 69 | CONFIG_DISPLAY_ROCKCHIP_HDMI=y |
| 70 | CONFIG_SPL_TINY_MEMSET=y |
| 71 | CONFIG_ERRNO_STR=y |