Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 4 | */ |
| 5 | #ifndef __CONFIG_SOCFPGA_SR1500_H__ |
| 6 | #define __CONFIG_SOCFPGA_SR1500_H__ |
| 7 | |
| 8 | #include <asm/arch/base_addr_ac5.h> |
| 9 | |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 10 | /* Memory configurations */ |
| 11 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */ |
| 12 | |
| 13 | /* Booting Linux */ |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 14 | #define CONFIG_LOADADDR 0x01000000 |
| 15 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 16 | |
| 17 | /* Ethernet on SoC (EMAC) */ |
| 18 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII |
| 19 | /* The PHY is autodetected, so no MII PHY address is needed here */ |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 20 | #define PHY_ANEG_TIMEOUT 8000 |
| 21 | |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 22 | /* Enable SPI NOR flash reset, needed for SPI booting */ |
| 23 | #define CONFIG_SPI_N25Q256A_RESET |
| 24 | |
| 25 | /* |
| 26 | * Bootcounter |
| 27 | */ |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 28 | #define CONFIG_SYS_BOOTCOUNT_BE |
| 29 | |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 30 | /* Environment setting for SPI flash */ |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 31 | #define CONFIG_SYS_REDUNDAND_ENVIRONMENT |
| 32 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) |
| 33 | #define CONFIG_ENV_SIZE (16 * 1024) |
Stefan Roese | 85e8439 | 2016-03-03 16:57:39 +0100 | [diff] [blame] | 34 | #define CONFIG_ENV_OFFSET 0x000e0000 |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 35 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE) |
Stefan Roese | 85e8439 | 2016-03-03 16:57:39 +0100 | [diff] [blame] | 36 | |
Marek Vasut | 4003fe2 | 2016-02-26 19:11:30 +0100 | [diff] [blame] | 37 | /* The rest of the configuration is shared */ |
| 38 | #include <configs/socfpga_common.h> |
| 39 | |
Stefan Roese | bf5ed2e | 2015-11-18 11:06:09 +0100 | [diff] [blame] | 40 | #endif /* __CONFIG_SOCFPGA_SR1500_H__ */ |