blob: e25bf99e1c23e3fe26f121f3f9f773c3f01e2458 [file] [log] [blame]
Andrej Rosanofddfa9c2015-04-08 18:56:30 +02001/*
2 * USB armory MkI board configuration settings
3 * http://inversepath.com/usbarmory
4 *
5 * Copyright (C) 2015, Inverse Path
6 * Andrej Rosano <andrej@inversepath.com>
7 *
8 * SPDX-License-Identifier:|____GPL-2.0+
9 */
10
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
Gong Qianyu52de2e52015-10-26 19:47:42 +080014#define CONFIG_SYS_FSL_CLK
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020015#define CONFIG_MXC_GPIO
16
17#include <asm/arch/imx-regs.h>
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020018
19#include <config_distro_defaults.h>
20
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020021/* U-Boot environment */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020022#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
23#define CONFIG_ENV_SIZE (8 * 1024)
24#define CONFIG_ENV_IS_IN_MMC
25#define CONFIG_SYS_MMC_ENV_DEV 0
26
27/* U-Boot general configurations */
28#define CONFIG_SYS_CBSIZE 512
29#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
30#define CONFIG_SYS_MAXARGS 16
31#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
32
33/* UART */
34#define CONFIG_MXC_UART
35#define CONFIG_MXC_UART_BASE UART1_BASE
36#define CONFIG_CONS_INDEX 1
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020037
38/* SD/MMC */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020039#define CONFIG_FSL_ESDHC
40#define CONFIG_SYS_FSL_ESDHC_ADDR 0
41#define CONFIG_SYS_FSL_ESDHC_NUM 1
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020042
43/* USB */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020044#define CONFIG_USB_EHCI_MX5
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020045#define CONFIG_MXC_USB_PORT 1
46#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
47#define CONFIG_MXC_USB_FLAGS 0
48
49/* I2C */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020050#define CONFIG_SYS_I2C
51#define CONFIG_SYS_I2C_MXC
Albert ARIBAUD \\(3ADEV\\)eb943872015-09-21 22:43:38 +020052#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
53#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020054
55/* Fuse */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020056#define CONFIG_FSL_IIM
57
Andrej Rosanof079e0d2016-06-20 17:21:48 +020058/* U-Boot memory offsets */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020059#define CONFIG_LOADADDR 0x72000000
60#define CONFIG_SYS_TEXT_BASE 0x77800000
61#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
Andrej Rosanof079e0d2016-06-20 17:21:48 +020062
63/* Linux boot */
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020064#define CONFIG_HOSTNAME usbarmory
65#define CONFIG_BOOTCOMMAND \
66 "run distro_bootcmd; " \
67 "setenv bootargs console=${console} ${bootargs_default}; " \
Andrej Rosanof079e0d2016-06-20 17:21:48 +020068 "ext2load mmc 0:1 ${kernel_addr_r} /boot/zImage; " \
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020069 "ext2load mmc 0:1 ${fdt_addr_r} /boot/${fdtfile}; " \
Andrej Rosanof079e0d2016-06-20 17:21:48 +020070 "bootz ${kernel_addr_r} - ${fdt_addr_r}"
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020071
72#define BOOT_TARGET_DEVICES(func) func(MMC, mmc, 0)
73
74#include <config_distro_bootcmd.h>
75
76#define MEM_LAYOUT_ENV_SETTINGS \
77 "kernel_addr_r=0x70800000\0" \
78 "fdt_addr_r=0x71000000\0" \
79 "scriptaddr=0x70800000\0" \
80 "pxefile_addr_r=0x70800000\0" \
81 "ramdisk_addr_r=0x73000000\0"
82
83#define CONFIG_EXTRA_ENV_SETTINGS \
84 MEM_LAYOUT_ENV_SETTINGS \
85 "bootargs_default=root=/dev/mmcblk0p1 rootwait rw\0" \
86 "fdtfile=imx53-usbarmory.dtb\0" \
87 "console=ttymxc0,115200\0" \
88 BOOTENV
89
Andrej Rosanobab77d02016-06-20 17:21:49 +020090#ifndef CONFIG_CMDLINE
91#define CONFIG_BOOTARGS "console=ttymxc0,115200 root=/dev/mmcblk0p1 rootwait rw"
92#define USBARMORY_FIT_PATH "/boot/usbarmory.itb"
93#define USBARMORY_FIT_ADDR "0x70800000"
94#endif
95
Andrej Rosanofddfa9c2015-04-08 18:56:30 +020096/* Physical Memory Map */
97#define CONFIG_NR_DRAM_BANKS 1
98#define PHYS_SDRAM CSD0_BASE_ADDR
99#define PHYS_SDRAM_SIZE (gd->ram_size)
100
101#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
102#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
103#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
104
105#define CONFIG_SYS_INIT_SP_OFFSET \
106 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
107#define CONFIG_SYS_INIT_SP_ADDR \
108 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
109
110#define CONFIG_SYS_MEMTEST_START 0x70000000
111#define CONFIG_SYS_MEMTEST_END 0x90000000
112
113#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
114
115#endif /* __CONFIG_H */