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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Tom Rinia2f4c912013-08-09 11:22:17 -04002/*
3 * ti_armv7_common.h
4 *
5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
6 *
Tom Rinia2f4c912013-08-09 11:22:17 -04007 * The various ARMv7 SoCs from TI all share a number of IP blocks when
8 * implementing a given feature. Rather than define these in every
9 * board or even SoC common file, we define a common file to be re-used
10 * in all cases. While technically true that some of these details are
11 * configurable at the board design, they are common throughout SoC
12 * reference platforms as well as custom designs and become de facto
13 * standards.
14 */
15
16#ifndef __CONFIG_TI_ARMV7_COMMON_H__
17#define __CONFIG_TI_ARMV7_COMMON_H__
18
Tom Rinia2f4c912013-08-09 11:22:17 -040019/*
Tom Rini96886f22014-03-28 15:03:29 -040020 * We setup defaults based on constraints from the Linux kernel, which should
21 * also be safe elsewhere. We have the default load at 32MB into DDR (for
22 * the kernel), FDT above 128MB (the maximum location for the end of the
23 * kernel), and the ramdisk 512KB above that (allowing for hopefully never
24 * seen large trees). We say all of this must be within the first 256MB
25 * as that will normally be within the kernel lowmem and thus visible via
26 * bootm_size and we only run on platforms with 256MB or more of memory.
Sam Protsenko1651ee12020-01-24 17:53:49 +020027 *
28 * As a temporary storage for DTBO blobs (which should be applied into DTB
29 * blob), we use the location 15.5 MB above the ramdisk. If someone wants to
30 * use ramdisk bigger than 15.5 MB, then DTBO can be loaded and applied to DTB
31 * blob before loading the ramdisk, as DTBO location is only used as a temporary
32 * storage, and can be re-used after 'fdt apply' command is done.
Tom Rinia2f4c912013-08-09 11:22:17 -040033 */
Tom Rini96886f22014-03-28 15:03:29 -040034#define DEFAULT_LINUX_BOOT_ENV \
35 "loadaddr=0x82000000\0" \
36 "kernel_addr_r=0x82000000\0" \
37 "fdtaddr=0x88000000\0" \
Sam Protsenko1651ee12020-01-24 17:53:49 +020038 "dtboaddr=0x89000000\0" \
Tom Rini96886f22014-03-28 15:03:29 -040039 "fdt_addr_r=0x88000000\0" \
Amjad Ouled-Ameur4d797722021-10-29 16:08:17 +020040 "fdtoverlay_addr_r=0x89000000\0" \
Tom Rini96886f22014-03-28 15:03:29 -040041 "rdaddr=0x88080000\0" \
42 "ramdisk_addr_r=0x88080000\0" \
Sjoerd Simons3a3b3d12015-08-28 15:01:55 +020043 "scriptaddr=0x80000000\0" \
44 "pxefile_addr_r=0x80100000\0" \
Lokesh Vutlaf01f8b32016-11-29 11:57:59 +053045 "bootm_size=0x10000000\0" \
46 "boot_fdt=try\0"
Tom Rinia2f4c912013-08-09 11:22:17 -040047
Lokesh Vutlac2913ac2016-11-29 11:58:00 +053048#define DEFAULT_FIT_TI_ARGS \
49 "boot_fit=0\0" \
Andrew F. Davis5589be62019-08-12 15:59:54 -040050 "addr_fit=0x90000000\0" \
Andrew F. Davis77c875c2019-08-12 15:59:55 -040051 "name_fit=fitImage\0" \
52 "update_to_fit=setenv loadaddr ${addr_fit}; setenv bootfile ${name_fit}\0" \
Andrew F. Davisc21e8192019-08-26 17:51:00 -040053 "get_overlaystring=" \
Suman Annaad30ac32020-04-24 13:39:52 -050054 "for overlay in $name_overlays;" \
Andrew F. Davisc21e8192019-08-26 17:51:00 -040055 "do;" \
56 "setenv overlaystring ${overlaystring}'#'${overlay};" \
57 "done;\0" \
Romain Naoura9c7f1c2022-02-10 23:13:36 +010058 "run_fit=bootm ${addr_fit}#conf-${fdtfile}${overlaystring}\0" \
Lokesh Vutlac2913ac2016-11-29 11:58:00 +053059
Tom Rinia2f4c912013-08-09 11:22:17 -040060/*
Enric Balletbò i Serra07322c52013-12-06 21:30:21 +010061 * DDR information. If the CONFIG_NR_DRAM_BANKS is not defined,
62 * we say (for simplicity) that we have 1 bank, always, even when
63 * we have more. We always start at 0x80000000, and we place the
64 * initial stack pointer in our SRAM. Otherwise, we can define
65 * CONFIG_NR_DRAM_BANKS before including this file.
Tom Rinia2f4c912013-08-09 11:22:17 -040066 */
Tom Rinia2f4c912013-08-09 11:22:17 -040067#define CONFIG_SYS_SDRAM_BASE 0x80000000
Nishanth Menonb4471512015-07-22 18:05:45 -050068
69#ifndef CONFIG_SYS_INIT_SP_ADDR
Tom Rinia2f4c912013-08-09 11:22:17 -040070#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
71 GENERATED_GBL_DATA_SIZE)
Nishanth Menonb4471512015-07-22 18:05:45 -050072#endif
Tom Rinia2f4c912013-08-09 11:22:17 -040073
Jean-Jacques Hiblot52a51512018-12-07 14:50:49 +010074/* If DM_I2C, enable non-DM I2C support */
Tom Rinia2f4c912013-08-09 11:22:17 -040075
Tom Rinia2f4c912013-08-09 11:22:17 -040076/*
Tom Rinia2f4c912013-08-09 11:22:17 -040077 * The following are general good-enough settings for U-Boot. We set a
78 * large malloc pool as we generally have a lot of DDR, and we opt for
79 * function over binary size in the main portion of U-Boot as this is
80 * generally easily constrained later if needed. We enable the config
81 * options that give us information in the environment about what board
82 * we are on so we do not need to rely on the command prompt. We set a
83 * console baudrate of 115200 and use the default baud rate table.
84 */
Tom Rinic5e96362013-08-20 08:53:49 -040085
86/* As stated above, the following choices are optional. */
Tom Rinia2f4c912013-08-09 11:22:17 -040087
Tom Rinia2f4c912013-08-09 11:22:17 -040088/* Console I/O Buffer Size */
Tom Rinia2f4c912013-08-09 11:22:17 -040089/*
90 * When we have SPI, NOR or NAND flash we expect to be making use of
91 * mtdparts, both for ease of use in U-Boot and for passing information
92 * on to the Linux kernel.
93 */
Tom Rinia2f4c912013-08-09 11:22:17 -040094
Tom Rinia2f4c912013-08-09 11:22:17 -040095/*
Tom Rinia2f4c912013-08-09 11:22:17 -040096 * Our platforms make use of SPL to initalize the hardware (primarily
Andrew F. Davise2f61e72016-08-30 14:06:28 -050097 * memory) enough for full U-Boot to be loaded. We make use of the general
98 * SPL framework found under common/spl/. Given our generally common memory
99 * map, we set a number of related defaults and sizes here.
Tom Rinia2f4c912013-08-09 11:22:17 -0400100 */
Sourav Poddar5248bba2014-05-19 16:53:37 -0400101#if !defined(CONFIG_NOR_BOOT) && \
102 !(defined(CONFIG_QSPI_BOOT) && defined(CONFIG_AM43XX))
Andrew F. Davise2f61e72016-08-30 14:06:28 -0500103
104/*
105 * We also support Falcon Mode so that the Linux kernel can be booted
106 * directly from SPL. This is not currently available on HS devices.
107 */
Tom Rinia2f4c912013-08-09 11:22:17 -0400108
109/*
Tom Rinibe737992014-07-18 11:51:32 -0400110 * Place the image at the start of the ROM defined image space (per
111 * CONFIG_SPL_TEXT_BASE and we limit our size to the ROM-defined
Tom Rinicfff4aa2016-08-26 13:30:43 -0400112 * downloaded image area minus 1KiB for scratch space. We initalize DRAM as
113 * soon as we can so that we can place stack, malloc and BSS there. We load
114 * U-Boot itself into memory at 0x80800000 for legacy reasons (to not conflict
115 * with older SPLs). We have our BSS be placed 2MiB after this, to allow for
116 * the default Linux kernel address of 0x80008000 to work with most sized
117 * kernels, in the Falcon Mode case. We have the SPL malloc pool at the end
118 * of the BSS area. We suggest that the stack be placed at 32MiB after the
119 * start of DRAM to allow room for all of the above (handled in Kconfig).
Tom Rinia2f4c912013-08-09 11:22:17 -0400120 */
Tom Rinie10247f2014-04-03 15:17:15 -0400121#ifndef CONFIG_SPL_BSS_START_ADDR
Tom Rinia2f4c912013-08-09 11:22:17 -0400122#define CONFIG_SPL_BSS_START_ADDR 0x80a00000
Tom Rinie10247f2014-04-03 15:17:15 -0400123#endif
124#ifndef CONFIG_SYS_SPL_MALLOC_START
Tom Rinia2f4c912013-08-09 11:22:17 -0400125#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
126 CONFIG_SPL_BSS_MAX_SIZE)
Tom Rinibc3a5572016-09-19 13:05:34 -0400127#define CONFIG_SYS_SPL_MALLOC_SIZE SZ_8M
Tom Rinie10247f2014-04-03 15:17:15 -0400128#endif
Tom Rinicfff4aa2016-08-26 13:30:43 -0400129
Tom Rinia2f4c912013-08-09 11:22:17 -0400130#ifdef CONFIG_SPL_OS_BOOT
Tom Rinia2f4c912013-08-09 11:22:17 -0400131/* FAT */
Tom Rinia2f4c912013-08-09 11:22:17 -0400132
133/* RAW SD card / eMMC */
Jean-Jacques Hiblota0900532017-05-24 12:08:27 +0200134#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x1500 /* address 0x2A0000 */
135#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS 0x200 /* 256KiB */
Tom Rinia2f4c912013-08-09 11:22:17 -0400136#endif
137
Tom Rinif48e5ee2013-08-20 08:53:44 -0400138/* General parts of the framework, required. */
Tom Rinia2f4c912013-08-09 11:22:17 -0400139
Miquel Raynald0935362019-10-03 19:50:03 +0200140#ifdef CONFIG_MTD_RAW_NAND
Tom Rinia2f4c912013-08-09 11:22:17 -0400141#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
Tom Rinia2f4c912013-08-09 11:22:17 -0400142#endif
143#endif /* !CONFIG_NOR_BOOT */
144
Cooper Jr., Franklin07610ab2015-04-21 07:51:04 -0500145/* Generic Environment Variables */
146
147#ifdef CONFIG_CMD_NET
148#define NETARGS \
149 "static_ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}" \
150 "::off\0" \
151 "nfsopts=nolock\0" \
152 "rootpath=/export/rootfs\0" \
153 "netloadimage=tftp ${loadaddr} ${bootfile}\0" \
154 "netloadfdt=tftp ${fdtaddr} ${fdtfile}\0" \
155 "netargs=setenv bootargs console=${console} " \
156 "${optargs} " \
157 "root=/dev/nfs " \
158 "nfsroot=${serverip}:${rootpath},${nfsopts} rw " \
159 "ip=dhcp\0" \
160 "netboot=echo Booting from network ...; " \
161 "setenv autoload no; " \
162 "dhcp; " \
163 "run netloadimage; " \
164 "run netloadfdt; " \
165 "run netargs; " \
166 "bootz ${loadaddr} - ${fdtaddr}\0"
Cooper Jr., Franklindcee9cf2015-06-10 08:54:02 -0500167#else
168#define NETARGS ""
Cooper Jr., Franklin07610ab2015-04-21 07:51:04 -0500169#endif
170
Tom Rinia2f4c912013-08-09 11:22:17 -0400171#endif /* __CONFIG_TI_ARMV7_COMMON_H__ */