| Nicolas Ferre | 8ba10c7 | 2019-08-08 07:48:26 +0000 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Configuration file for the SAMA5D27 WLSOM1 EK Board. |
| 4 | * |
| 5 | * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries |
| 6 | * |
| 7 | * Author: Nicolas Ferre <nicolas.ferre@microcihp.com> |
| 8 | */ |
| 9 | |
| 10 | #ifndef __CONFIG_H |
| 11 | #define __CONFIG_H |
| 12 | |
| 13 | #include "at91-sama5_common.h" |
| 14 | |
| 15 | #undef CONFIG_SYS_AT91_MAIN_CLOCK |
| 16 | #define CONFIG_SYS_AT91_MAIN_CLOCK 24000000 /* from 24 MHz crystal */ |
| 17 | |
| 18 | /* SDRAM */ |
| 19 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 20 | #define CONFIG_SYS_SDRAM_SIZE 0x10000000 |
| 21 | |
| 22 | #define CONFIG_SYS_INIT_SP_ADDR \ |
| 23 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
| 24 | |
| Eugen Hristev | 1d15212 | 2019-08-08 07:48:35 +0000 | [diff] [blame] | 25 | /* SPL */ |
| Tom Rini | 89ca343 | 2022-05-24 13:11:41 -0400 | [diff] [blame^] | 26 | #define CONFIG_SPL_STACK 0x218000 |
| Eugen Hristev | 1d15212 | 2019-08-08 07:48:35 +0000 | [diff] [blame] | 27 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| Eugen Hristev | 1d15212 | 2019-08-08 07:48:35 +0000 | [diff] [blame] | 28 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 29 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 30 | |
| 31 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| Nicolas Ferre | 8ba10c7 | 2019-08-08 07:48:26 +0000 | [diff] [blame] | 32 | |
| Nicolas Ferre | 8ba10c7 | 2019-08-08 07:48:26 +0000 | [diff] [blame] | 33 | #endif |