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Stefan Roese09554022005-11-30 13:06:40 +01001/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
Stefan Roese09554022005-11-30 13:06:40 +010024#include <common.h>
25#include <asm/processor.h>
26#include <asm/immap_85xx.h>
27#include <asm/processor.h>
28#include <asm/mmu.h>
Stefan Roese09554022005-11-30 13:06:40 +010029
30struct sdram_conf_s {
31 unsigned long size;
32 unsigned long reg;
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020033#ifdef CONFIG_TQM8548
34 unsigned long refresh;
35#endif /* CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +010036};
37
38typedef struct sdram_conf_s sdram_conf_t;
39
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020040#ifdef CONFIG_TQM8548
41sdram_conf_t ddr_cs_conf[] = {
42 {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */
43 {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */
44 {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */
45};
46#else /* !CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +010047sdram_conf_t ddr_cs_conf[] = {
48 {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */
49 {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */
50 {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +020051 {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */
Stefan Roese09554022005-11-30 13:06:40 +010052};
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020053#endif /* CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +010054
55#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
56
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +020057int cas_latency (void);
Stefan Roese09554022005-11-30 13:06:40 +010058
59/*
60 * Autodetect onboard DDR SDRAM on 85xx platforms
61 *
62 * NOTE: Some of the hardcoded values are hardware dependant,
63 * so this should be extended for other future boards
64 * using this routine!
65 */
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +020066long int sdram_setup (int casl)
Stefan Roese09554022005-11-30 13:06:40 +010067{
68 int i;
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020069 volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020070#ifdef CONFIG_TQM8548
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020071 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020072#else /* !CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +010073 unsigned long cfg_ddr_timing1;
74 unsigned long cfg_ddr_mode;
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020075#endif /* CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +010076
77 /*
78 * Disable memory controller.
79 */
80 ddr->cs0_config = 0;
81 ddr->sdram_cfg = 0;
82
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020083#ifdef CONFIG_TQM8548
Wolfgang Grandegger89ad1852009-02-11 18:38:23 +010084 /* Timing and refresh settings for DDR2-533 and below */
85
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020086 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
87 ddr->cs0_config = ddr_cs_conf[0].reg;
Wolfgang Grandegger89ad1852009-02-11 18:38:23 +010088 ddr->timing_cfg_3 = 0x00020000;
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020089
90 /* TIMING CFG 1, 533MHz
91 * PRETOACT: 4 Clocks
92 * ACTTOPRE: 12 Clocks
93 * ACTTORW: 4 Clocks
94 * CASLAT: 4 Clocks
Wolfgang Grandegger89ad1852009-02-11 18:38:23 +010095 * REFREC: EXT_REFREC:REFREC 53 Clocks
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +020096 * WRREC: 4 Clocks
97 * ACTTOACT: 3 Clocks
98 * WRTORD: 2 Clocks
99 */
Wolfgang Grandegger89ad1852009-02-11 18:38:23 +0100100 ddr->timing_cfg_1 = 0x4C47D432;
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +0200101
102 /* TIMING CFG 2, 533MHz
103 * ADD_LAT: 3 Clocks
104 * CPO: READLAT + 1
105 * WR_LAT: 3 Clocks
106 * RD_TO_PRE: 2 Clocks
107 * WR_DATA_DELAY: 1/2 Clock
Wolfgang Grandegger89ad1852009-02-11 18:38:23 +0100108 * CKE_PLS: 3 Clock
109 * FOUR_ACT: 14 Clocks
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +0200110 */
Wolfgang Grandegger89ad1852009-02-11 18:38:23 +0100111 ddr->timing_cfg_2 = 0x331848CE;
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +0200112
113 /* DDR SDRAM Mode, 533MHz
114 * MRS: Extended Mode Register
115 * OUT: Outputs enabled
116 * RDQS: no
117 * DQS: enabled
118 * OCD: default state
119 * RTT: 75 Ohms
120 * Posted CAS: 3 Clocks
121 * ODS: reduced strength
122 * DLL: enabled
123 * MR: Mode Register
124 * PD: fast exit
125 * WR: 4 Clocks
126 * DLL: no DLL reset
127 * TM: normal
128 * CAS latency: 4 Clocks
129 * BT: sequential
130 * Burst length: 4
131 */
132 ddr->sdram_mode = 0x439E0642;
133
134 /* DDR SDRAM Interval, 533MHz
135 * REFINT: 1040 Clocks
136 * BSTOPRE: 256
137 */
138 ddr->sdram_interval = (1040 << 16) | 0x100;
139
140 /*
141 * workaround for erratum DD10 of MPC8458 family below rev. 2.0:
142 * DDR IO receiver must be set to an acceptable bias point by modifying
143 * a hidden register.
144 */
145 if (SVR_REV (get_svr ()) < 0x20) {
146 gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */
147 }
148
149 /* DDR SDRAM CFG 2
150 * FRC_SR: normal mode
151 * SR_IE: no self-refresh interrupt
152 * DLL_RST_DIS: don't care, leave at reset value
153 * DQS_CFG: differential DQS signals
154 * ODT_CFG: assert ODT to internal IOs only during reads to DRAM
155 * LVWx_CFG: don't care, leave at reset value
156 * NUM_PR: 1 refresh will be issued at a time
157 * DM_CFG: don't care, leave at reset value
158 * D_INIT: no data initialization
159 */
160 ddr->sdram_cfg_2 = 0x04401000;
161
162 /* DDR SDRAM MODE 2
163 * MRS: Extended Mode Register 2
164 */
165 ddr->sdram_mode_2 = 0x8000C000;
166
167 /* DDR SDRAM CLK CNTL
168 * CLK_ADJUST: 1/2 Clock 0x02000000
169 * CLK_ADJUST: 5/8 Clock 0x02800000
170 */
171 ddr->sdram_clk_cntl = 0x02800000;
172
173 /* wait for clock stabilization */
174 asm ("sync;isync;msync");
175 udelay(1000);
176
177 /* DDR SDRAM CLK CNTL
178 * MEM_EN: enabled
179 * SREN: don't care, leave at reset value
180 * ECC_EN: no error report
181 * RD_EN: no register DIMMs
182 * SDRAM_TYPE: DDR2
183 * DYN_PWR: no power management
184 * 32_BE: don't care, leave at reset value
185 * 8_BE: 4 beat burst
186 * NCAP: don't care, leave at reset value
187 * 2T_EN: 1T Timing
188 * BA_INTLV_CTL: no interleaving
189 * x32_EN: x16 organization
190 * PCHB8: MA[10] for auto-precharge
191 * HSE: half strength for single and 2-layer stacks
192 * (full strength for 3- and 4-layer stacks no yet considered)
193 * MEM_HALT: no halt
194 * BI: automatic initialization
195 */
196 ddr->sdram_cfg = 0x83000008;
197 asm ("sync; isync; msync");
198 udelay(1000);
199
200#else /* !CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +0100201 switch (casl) {
202 case 20:
203 cfg_ddr_timing1 = 0x47405331 | (3 << 16);
204 cfg_ddr_mode = 0x40020002 | (2 << 4);
205 break;
206
207 case 25:
208 cfg_ddr_timing1 = 0x47405331 | (4 << 16);
209 cfg_ddr_mode = 0x40020002 | (6 << 4);
210 break;
211
212 case 30:
213 default:
214 cfg_ddr_timing1 = 0x47405331 | (5 << 16);
215 cfg_ddr_mode = 0x40020002 | (3 << 4);
216 break;
217 }
218
219 ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
220 ddr->cs0_config = ddr_cs_conf[0].reg;
221 ddr->timing_cfg_1 = cfg_ddr_timing1;
222 ddr->timing_cfg_2 = 0x00000800; /* P9-45,may need tuning */
223 ddr->sdram_mode = cfg_ddr_mode;
224 ddr->sdram_interval = 0x05160100; /* autocharge,no open page */
225 ddr->err_disable = 0x0000000D;
226
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200227 asm ("sync; isync; msync");
228 udelay (1000);
Stefan Roese09554022005-11-30 13:06:40 +0100229
230 ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */
231 asm ("sync; isync; msync");
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200232 udelay (1000);
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +0200233#endif /* CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +0100234
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200235 for (i = 0; i < N_DDR_CS_CONF; i++) {
Stefan Roese09554022005-11-30 13:06:40 +0100236 ddr->cs0_config = ddr_cs_conf[i].reg;
237
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200238 if (get_ram_size (0, ddr_cs_conf[i].size) ==
239 ddr_cs_conf[i].size) {
Stefan Roese09554022005-11-30 13:06:40 +0100240 /*
Wolfgang Grandegger6d571542008-06-05 13:12:04 +0200241 * size detected -> set Chip Select Bounds Register
Stefan Roese09554022005-11-30 13:06:40 +0100242 */
Wolfgang Grandegger6d571542008-06-05 13:12:04 +0200243 ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
244
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +0200245 break;
Stefan Roese09554022005-11-30 13:06:40 +0100246 }
247 }
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +0200248
249#ifdef CONFIG_TQM8548
250 if (i < N_DDR_CS_CONF) {
251 /* Adjust refresh rate for DDR2 */
252
253 ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
254
255 ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
256 (ddr_cs_conf[i].refresh & 0x0000F000);
257
258 return ddr_cs_conf[i].size;
259 }
260#endif /* CONFIG_TQM8548 */
Stefan Roese09554022005-11-30 13:06:40 +0100261
Wolfgang Grandegger328c6ec2008-06-05 13:12:07 +0200262 /* return size if detected, else return 0 */
263 return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
Stefan Roese09554022005-11-30 13:06:40 +0100264}
265
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200266void board_add_ram_info (int use_default)
Stefan Roese09554022005-11-30 13:06:40 +0100267{
268 int casl;
269
270 if (use_default)
271 casl = CONFIG_DDR_DEFAULT_CL;
272 else
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200273 casl = cas_latency ();
Stefan Roese09554022005-11-30 13:06:40 +0100274
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200275 puts (" (CL=");
Stefan Roese09554022005-11-30 13:06:40 +0100276 switch (casl) {
277 case 20:
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200278 puts ("2)");
Stefan Roese09554022005-11-30 13:06:40 +0100279 break;
280
281 case 25:
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200282 puts ("2.5)");
Stefan Roese09554022005-11-30 13:06:40 +0100283 break;
284
285 case 30:
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200286 puts ("3)");
Stefan Roese09554022005-11-30 13:06:40 +0100287 break;
288 }
289}
290
Becky Brucebd99ae72008-06-09 16:03:40 -0500291phys_size_t initdram (int board_type)
Stefan Roese09554022005-11-30 13:06:40 +0100292{
293 long dram_size = 0;
294 int casl;
295
296#if defined(CONFIG_DDR_DLL)
297 /*
298 * This DLL-Override only used on TQM8540 and TQM8560
299 */
300 {
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200301 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200302 int i, x;
Stefan Roese09554022005-11-30 13:06:40 +0100303
304 x = 10;
305
306 /*
307 * Work around to stabilize DDR DLL
308 */
309 gur->ddrdllcr = 0x81000000;
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200310 asm ("sync; isync; msync");
Stefan Roese09554022005-11-30 13:06:40 +0100311 udelay (200);
312 while (gur->ddrdllcr != 0x81000100) {
313 gur->devdisr = gur->devdisr | 0x00010000;
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200314 asm ("sync; isync; msync");
315 for (i = 0; i < x; i++)
Stefan Roese09554022005-11-30 13:06:40 +0100316 ;
317 gur->devdisr = gur->devdisr & 0xfff7ffff;
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200318 asm ("sync; isync; msync");
Stefan Roese09554022005-11-30 13:06:40 +0100319 x++;
320 }
321 }
322#endif
323
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200324 casl = cas_latency ();
325 dram_size = sdram_setup (casl);
Stefan Roese09554022005-11-30 13:06:40 +0100326 if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
327 /*
328 * Try again with default CAS latency
329 */
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200330 puts ("Problem with CAS lantency");
331 board_add_ram_info (1);
332 puts (", using default CL!\n");
Stefan Roese09554022005-11-30 13:06:40 +0100333 casl = CONFIG_DDR_DEFAULT_CL;
Wolfgang Grandegger9039ce12008-06-05 13:12:00 +0200334 dram_size = sdram_setup (casl);
335 puts (" ");
Stefan Roese09554022005-11-30 13:06:40 +0100336 }
337
338 return dram_size;
339}
340
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200341#if defined(CONFIG_SYS_DRAM_TEST)
Stefan Roese09554022005-11-30 13:06:40 +0100342int testdram (void)
343{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200344 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
345 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
Stefan Roese09554022005-11-30 13:06:40 +0100346 uint *p;
347
348 printf ("SDRAM test phase 1:\n");
349 for (p = pstart; p < pend; p++)
350 *p = 0xaaaaaaaa;
351
352 for (p = pstart; p < pend; p++) {
353 if (*p != 0xaaaaaaaa) {
354 printf ("SDRAM test fails at: %08x\n", (uint) p);
355 return 1;
356 }
357 }
358
359 printf ("SDRAM test phase 2:\n");
360 for (p = pstart; p < pend; p++)
361 *p = 0x55555555;
362
363 for (p = pstart; p < pend; p++) {
364 if (*p != 0x55555555) {
365 printf ("SDRAM test fails at: %08x\n", (uint) p);
366 return 1;
367 }
368 }
369
370 printf ("SDRAM test passed.\n");
371 return 0;
372}
373#endif