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git01.mediatek.com / filogic / uboot / 89a90d022a72f1bf4585a75220acec6a4f9e78bb / . / arch / arm / dts / imx8mp-debix-model-a.dts
blob: 58dae612b4b8787bd29f8efe8b1840d61b8617b1 [file] [log] [blame]
Gilles Talis42a56352023-12-13 09:29:40 -0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 * Copyright 2022 Ideas on Board Oy
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/leds/common.h>
11#include <dt-bindings/usb/pd.h>
12
13#include "imx8mp.dtsi"
14
15/ {
16 model = "Polyhex Debix Model A i.MX8MPlus board";
17 compatible = "polyhex,imx8mp-debix-model-a", "polyhex,imx8mp-debix", "fsl,imx8mp";
18
19 chosen {
20 stdout-path = &uart2;
21 };
22
23 leds {
24 compatible = "gpio-leds";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_gpio_led>;
27
28 led-0 {
29 function = LED_FUNCTION_POWER;
30 color = <LED_COLOR_ID_RED>;
31 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
32 default-state = "on";
33 };
34 };
35
36 reg_usdhc2_vmmc: regulator-usdhc2 {
37 compatible = "regulator-fixed";
38 pinctrl-names = "default";
39 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
40 regulator-name = "VSD_3V3";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
44 enable-active-high;
45 };
46};
47
48&A53_0 {
49 cpu-supply = <&buck2>;
50};
51
52&A53_1 {
53 cpu-supply = <&buck2>;
54};
55
56&A53_2 {
57 cpu-supply = <&buck2>;
58};
59
60&A53_3 {
61 cpu-supply = <&buck2>;
62};
63
64&eqos {
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_eqos>;
67 phy-connection-type = "rgmii-id";
68 phy-handle = <&ethphy0>;
69 status = "okay";
70
71 mdio {
72 compatible = "snps,dwmac-mdio";
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 ethphy0: ethernet-phy@0 { /* RTL8211E */
77 compatible = "ethernet-phy-ieee802.3-c22";
78 reg = <0>;
79 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
80 reset-assert-us = <20>;
81 reset-deassert-us = <200000>;
82 };
83 };
84};
85
86&i2c1 {
87 clock-frequency = <400000>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&pinctrl_i2c1>;
90 status = "okay";
91
92 pmic: pmic@25 {
93 compatible = "nxp,pca9450c";
94 reg = <0x25>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_pmic>;
97 interrupt-parent = <&gpio1>;
98 interrupts = <3 IRQ_TYPE_EDGE_RISING>;
99
100 regulators {
101 buck1: BUCK1 {
102 regulator-name = "BUCK1";
103 regulator-min-microvolt = <600000>;
104 regulator-max-microvolt = <2187500>;
105 regulator-boot-on;
106 regulator-always-on;
107 regulator-ramp-delay = <3125>;
108 };
109
110 buck2: BUCK2 {
111 regulator-name = "BUCK2";
112 regulator-min-microvolt = <600000>;
113 regulator-max-microvolt = <2187500>;
114 regulator-boot-on;
115 regulator-always-on;
116 regulator-ramp-delay = <3125>;
117 nxp,dvs-run-voltage = <950000>;
118 nxp,dvs-standby-voltage = <850000>;
119 };
120
121 buck4: BUCK4{
122 regulator-name = "BUCK4";
123 regulator-min-microvolt = <600000>;
124 regulator-max-microvolt = <3400000>;
125 regulator-boot-on;
126 regulator-always-on;
127 };
128
129 buck5: BUCK5{
130 regulator-name = "BUCK5";
131 regulator-min-microvolt = <600000>;
132 regulator-max-microvolt = <3400000>;
133 regulator-boot-on;
134 regulator-always-on;
135 };
136
137 buck6: BUCK6 {
138 regulator-name = "BUCK6";
139 regulator-min-microvolt = <600000>;
140 regulator-max-microvolt = <3400000>;
141 regulator-boot-on;
142 regulator-always-on;
143 };
144
145 ldo1: LDO1 {
146 regulator-name = "LDO1";
147 regulator-min-microvolt = <1600000>;
148 regulator-max-microvolt = <3300000>;
149 regulator-boot-on;
150 regulator-always-on;
151 };
152
153 ldo2: LDO2 {
154 regulator-name = "LDO2";
155 regulator-min-microvolt = <800000>;
156 regulator-max-microvolt = <1150000>;
157 regulator-boot-on;
158 regulator-always-on;
159 };
160
161 ldo3: LDO3 {
162 regulator-name = "LDO3";
163 regulator-min-microvolt = <800000>;
164 regulator-max-microvolt = <3300000>;
165 regulator-boot-on;
166 regulator-always-on;
167 };
168
169 ldo4: LDO4 {
170 regulator-name = "LDO4";
171 regulator-min-microvolt = <800000>;
172 regulator-max-microvolt = <3300000>;
173 regulator-boot-on;
174 regulator-always-on;
175 };
176
177 ldo5: LDO5 {
178 regulator-name = "LDO5";
179 regulator-min-microvolt = <1800000>;
180 regulator-max-microvolt = <3300000>;
181 regulator-boot-on;
182 regulator-always-on;
183 };
184 };
185 };
186};
187
188&i2c2 {
189 clock-frequency = <100000>;
190 pinctrl-names = "default";
191 pinctrl-0 = <&pinctrl_i2c2>;
192 status = "okay";
193};
194
195&i2c3 {
196 clock-frequency = <400000>;
197 pinctrl-names = "default";
198 pinctrl-0 = <&pinctrl_i2c3>;
199 status = "okay";
200};
201
202&i2c4 {
203 clock-frequency = <100000>;
204 pinctrl-names = "default";
205 pinctrl-0 = <&pinctrl_i2c4>;
206 status = "okay";
207
208 eeprom@50 {
209 compatible = "atmel,24c02";
210 reg = <0x50>;
211 pagesize = <16>;
212 };
213
214 rtc@51 {
215 compatible = "haoyu,hym8563";
216 reg = <0x51>;
217 #clock-cells = <0>;
218 clock-frequency = <32768>;
219 clock-output-names = "xin32k";
220 interrupt-parent = <&gpio2>;
221 interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_rtc_int>;
224 };
225};
226
227&i2c6 {
228 clock-frequency = <400000>;
229 pinctrl-names = "default";
230 pinctrl-0 = <&pinctrl_i2c6>;
231 status = "okay";
232};
233
234&snvs_pwrkey {
235 status = "okay";
236};
237
238&uart2 {
239 /* console */
240 pinctrl-names = "default";
241 pinctrl-0 = <&pinctrl_uart2>;
242 status = "okay";
243};
244
245&uart3 {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_uart3>;
248 status = "okay";
249};
250
251&uart4 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_uart4>;
254 status = "okay";
255};
256
257/* SD Card */
258&usdhc2 {
259 pinctrl-names = "default", "state_100mhz", "state_200mhz";
260 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
261 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
262 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
263 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
264 vmmc-supply = <&reg_usdhc2_vmmc>;
265 bus-width = <4>;
266 status = "okay";
267};
268
269/* eMMC */
270&usdhc3 {
271 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
272 assigned-clock-rates = <400000000>;
273 pinctrl-names = "default", "state_100mhz", "state_200mhz";
274 pinctrl-0 = <&pinctrl_usdhc3>;
275 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
276 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
277 bus-width = <8>;
278 non-removable;
279 status = "okay";
280};
281
282&wdog1 {
283 pinctrl-names = "default";
284 pinctrl-0 = <&pinctrl_wdog>;
285 fsl,ext-reset-output;
286 status = "okay";
287};
288
289&iomuxc {
290 pinctrl_eqos: eqosgrp {
291 fsl,pins = <
292 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3
293 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3
294 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91
295 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91
296 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91
297 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91
298 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91
299 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91
300 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f
301 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f
302 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f
303 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f
304 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f
305 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f
306 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x1f
307 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x1f
308 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19
309 >;
310 };
311
312 pinctrl_fec: fecgrp {
313 fsl,pins = <
314 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3
315 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3
316 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91
317 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
318 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
319 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
320 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
321 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
322 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f
323 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f
324 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f
325 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f
326 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f
327 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f
328 MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x1f
329 MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x1f
330 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19
331 >;
332 };
333
334 pinctrl_gpio_led: gpioledgrp {
335 fsl,pins = <
336 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
337 >;
338 };
339
340 pinctrl_i2c1: i2c1grp {
341 fsl,pins = <
342 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
343 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
344 >;
345 };
346
347 pinctrl_i2c2: i2c2grp {
348 fsl,pins = <
349 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
350 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
351 >;
352 };
353
354 pinctrl_i2c3: i2c3grp {
355 fsl,pins = <
356 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
357 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
358 >;
359 };
360
361 pinctrl_i2c4: i2c4grp {
362 fsl,pins = <
363 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
364 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
365 >;
366 };
367
368 pinctrl_i2c6: i2c6grp {
369 fsl,pins = <
370 MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
371 MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
372 >;
373 };
374
375 pinctrl_pmic: pmicirqgrp {
376 fsl,pins = <
377 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
378 >;
379 };
380
381 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
382 fsl,pins = <
383 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
384 >;
385 };
386
387 pinctrl_rtc_int: rtcintgrp {
388 fsl,pins = <
389 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x140
390 >;
391 };
392
393 pinctrl_uart2: uart2grp {
394 fsl,pins = <
395 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f
396 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f
397 >;
398 };
399
400 pinctrl_uart3: uart3grp {
401 fsl,pins = <
402 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x49
403 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x49
404 >;
405 };
406
407 pinctrl_uart4: uart4grp {
408 fsl,pins = <
409 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x49
410 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x49
411 >;
412 };
413
414 pinctrl_usdhc2: usdhc2grp {
415 fsl,pins = <
416 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
417 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
418 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
419 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
420 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
421 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
422 >;
423 };
424
425 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
426 fsl,pins = <
427 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
428 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
429 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
430 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
431 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
432 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
433 >;
434 };
435
436 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
437 fsl,pins = <
438 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
439 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
440 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
441 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
442 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
443 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
444 >;
445 };
446
447 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
448 fsl,pins = <
449 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
450 >;
451 };
452
453 pinctrl_usdhc3: usdhc3grp {
454 fsl,pins = <
455 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
456 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
457 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
458 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
459 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
460 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
461 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
462 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
463 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
464 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
465 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
466 >;
467 };
468
469 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
470 fsl,pins = <
471 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
472 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
473 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
474 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
475 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
476 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
477 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
478 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
479 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
480 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
481 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
482 >;
483 };
484
485 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
486 fsl,pins = <
487 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
488 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
489 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
490 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
491 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
492 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
493 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
494 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
495 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
496 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
497 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
498 >;
499 };
500
501 pinctrl_wdog: wdoggrp {
502 fsl,pins = <
503 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
504 >;
505 };
506};
507