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git01.mediatek.com / filogic / uboot / 89a90d022a72f1bf4585a75220acec6a4f9e78bb / . / arch / arm / dts / fsl-imx8qxp-colibri.dts
blob: b479921aff9ad0c3a01ed9238e4b8fbbeea0f26e [file] [log] [blame]
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
6/dts-v1/;
7
8#include "fsl-imx8qxp.dtsi"
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]9
10/ {
Philippe Schenker336720f2020-08-28 21:08:05 +0300[diff] [blame]11 model = "Toradex Colibri iMX8X";
12 compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]13
14 chosen {
15 bootargs = "console=ttyLP3,115200 earlycon=lpuart32,0x5a090000,115200";
16 stdout-path = &lpuart3;
17 };
18
19 reg_usbh_vbus: regulator-usbh-vbus {
20 compatible = "regulator-fixed";
21 pinctrl-names = "default";
22 pinctrl-0 = <&pinctrl_usbh1_reg>;
23 regulator-name = "usbh_vbus";
24 regulator-min-microvolt = <5000000>;
25 regulator-max-microvolt = <5000000>;
26 gpio = <&gpio4 3 GPIO_ACTIVE_LOW>;
27 };
28};
29
30&iomuxc {
31 pinctrl-names = "default";
32 pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_hog2>;
33
Philippe Schenker336720f2020-08-28 21:08:05 +0300[diff] [blame]34 colibri-imx8x {
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]35 pinctrl_lpuart0: lpuart0grp {
36 fsl,pins = <
37 SC_P_UART0_RX_ADMA_UART0_RX 0x06000020
38 SC_P_UART0_TX_ADMA_UART0_TX 0x06000020
39 >;
40 };
41
42 pinctrl_lpuart3: lpuart3grp {
43 fsl,pins = <
44 SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
45 SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020
46 >;
47 };
48
49 pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
50 fsl,pins = <
51 SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 /* DTR */
52 SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x00000020 /* CTS */
53 SC_P_SAI1_RXC_LSIO_GPIO0_IO30 0x00000020 /* RTS */
54 SC_P_CSI_RESET_LSIO_GPIO3_IO03 0x00000020 /* DSR */
55 SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000020 /* DCD */
56 SC_P_CSI_EN_LSIO_GPIO3_IO02 0x00000020 /* RI */
57 >;
58 };
59
60 pinctrl_fec1: fec1grp {
61 fsl,pins = <
62 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 /* Use pads in 3.3V mode */
63 SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 /* Use pads in 3.3V mode */
64 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
65 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
66 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061
67 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
68 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061
69 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061
70 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061
71 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061
72 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061
73 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x00000061
74 >;
75 };
76
77 pinctrl_gpio_bl_on: gpio-bl-on {
78 fsl,pins = <
79 SC_P_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x00000040
80 >;
81 };
82
83 pinctrl_hog0: hog0grp {
84 fsl,pins = <
85 SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 /* Use pads in 3.3V mode */
86 >;
87 };
88
89 pinctrl_hog1: hog1grp {
90 fsl,pins = <
91 SC_P_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x00000020 /* 45 */
92 SC_P_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* 65 */
93 SC_P_CSI_D07_CI_PI_D09 0x00000061
94 SC_P_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x00000020 /* 69 */
95 SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13 0x00000020 /* 73 */
96 SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x00000020 /* 79 */
97 SC_P_CSI_D02_CI_PI_D04 0x00000061
98 SC_P_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* 85 */
99 SC_P_CSI_D06_CI_PI_D08 0x00000061
100 SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x00000020 /* 95 */
101 SC_P_SAI0_RXD_LSIO_GPIO0_IO27 0x00000020 /* 97 */
102 SC_P_CSI_D03_CI_PI_D05 0x00000061
103 SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x00000020 /* 99 */
104 SC_P_SAI0_TXFS_LSIO_GPIO0_IO28 0x00000020 /* 101 */
105 SC_P_CSI_D00_CI_PI_D02 0x00000061
106 SC_P_SAI0_TXD_LSIO_GPIO0_IO25 0x00000020 /* 103 */
107 SC_P_CSI_D01_CI_PI_D03 0x00000061
108 SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x00000020 /* 105 */
109 SC_P_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x00000020 /* 107 */
110 SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x00000020 /* 127 */
111 SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x00000020 /* 131 */
112 SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000020 /* 133 */
113 SC_P_CSI_PCLK_LSIO_GPIO3_IO00 0x00000020 /* 96 */
114 SC_P_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x00000020 /* 98 */
115 SC_P_SAI1_RXFS_LSIO_GPIO0_IO31 0x00000020 /* 100 */
116 SC_P_QSPI0B_DQS_LSIO_GPIO3_IO22 0x00000020 /* 102 */
117 SC_P_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x00000020 /* 104 */
118 SC_P_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x00000020 /* 106 */
119 >;
120 };
121
122 pinctrl_hog2: hog2grp {
123 fsl,pins = <
124 SC_P_CSI_MCLK_LSIO_GPIO3_IO01 0x00000020 /* 75 */
125 SC_P_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x00000020 /* 77 */
126 SC_P_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x00000020 /* 89 */
127 SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x00000020 /* 93 */
128 >;
129 };
130
Oleksandr Suvorov70be7a22021-11-21 18:05:17 +0200[diff] [blame]131 /* On Module I2C */
132 pinctrl_i2c0: i2c0grp {
133 fsl,pins = <
134 SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
135 SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
136 >;
137 };
138
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]139 /* Off Module I2C */
140 pinctrl_i2c1: i2c1grp {
141 fsl,pins = <
142 SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021
143 SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021
144 >;
145 };
146
147 /*INT*/
148 pinctrl_usb3503a: usb3503a-grp {
149 fsl,pins = <
150 SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x00000061
151 >;
152 };
153
154 pinctrl_usbc_det: usbc-det {
155 fsl,pins = <
156 SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040
157 >;
158 };
159
160 pinctrl_usbh1_reg: usbh1-reg {
161 fsl,pins = <
162 SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040
163 >;
164 };
165
166 pinctrl_usdhc1: usdhc1grp {
167 fsl,pins = <
168 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
169 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
170 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
171 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
172 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
173 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
174 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
175 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
176 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
177 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
178 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
179 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
180 >;
181 };
182
183 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
184 fsl,pins = <
185 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
186 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
187 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
188 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
189 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
190 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
191 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
192 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
193 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
194 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
195 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
196 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
197 >;
198 };
199
200 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
201 fsl,pins = <
202 SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
203 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
204 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
205 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
206 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
207 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
208 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
209 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
210 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
211 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
212 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
213 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
214 >;
215 };
216
217 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
218 fsl,pins = <
219 SC_P_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021
220 >;
221 };
222
223 pinctrl_usdhc2: usdhc2grp {
224 fsl,pins = <
225 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
226 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
227 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
228 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
229 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
230 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
231 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
232 >;
233 };
234
235 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
236 fsl,pins = <
237 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
238 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
239 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
240 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
241 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
242 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
243 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
244 >;
245 };
246
247 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
248 fsl,pins = <
249 SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
250 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
251 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
252 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
253 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
254 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
255 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
256 >;
257 };
258 };
259};
260
261&lpuart0 {
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_lpuart0>;
264 status = "okay";
265};
266
267&lpuart3 {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
270 status = "okay";
271};
272
273&gpio0 {
274 status = "okay";
275};
276
277&gpio1 {
278 status = "okay";
279};
280
281&gpio3 {
282 status = "okay";
283};
284
285&gpio4 {
286 status = "okay";
287};
288
289&fec1 {
290 phy-handle = <&ethphy0>;
291 phy-mode = "rmii";
292 pinctrl-names = "default";
293 pinctrl-0 = <&pinctrl_fec1>;
294 status = "okay";
295
296 mdio {
297 #address-cells = <1>;
298 #size-cells = <0>;
299
300 ethphy0: ethernet-phy@2 {
301 compatible = "ethernet-phy-ieee802.3-c22";
302 max-speed = <100>;
303 reg = <2>;
304 };
305 };
306};
307
Oleksandr Suvorov70be7a22021-11-21 18:05:17 +0200[diff] [blame]308&i2c0 {
309 #address-cells = <1>;
310 #size-cells = <0>;
311 clock-frequency = <100000>;
312 pinctrl-names = "default";
313 pinctrl-0 = <&pinctrl_i2c0>;
314 status = "okay";
315
316 /* GPIO expander */
317 gpio_expander_43: gpio-expander@43 {
318 compatible = "fcs,fxl6408";
319 gpio-controller;
320 #gpio-cells = <2>;
321 reg = <0x43>;
Oleksandr Suvorov70be7a22021-11-21 18:05:17 +0200[diff] [blame]322 };
323};
324
Marcel Ziswiler99d768b2019-05-31 18:56:39 +0300[diff] [blame]325&i2c1 {
326 #address-cells = <1>;
327 #size-cells = <0>;
328 clock-frequency = <100000>;
329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_i2c1>;
331 status = "okay";
332};
333
334&usdhc1 {
335 bus-width = <8>;
336 non-removable;
337 pinctrl-names = "default", "state_100mhz", "state_200mhz";
338 pinctrl-0 = <&pinctrl_usdhc1>;
339 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
340 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
341 status = "okay";
342};
343
344&usdhc2 {
345 bus-width = <4>;
346 cd-gpios = <&gpio3 9 GPIO_ACTIVE_LOW>;
347 pinctrl-names = "default", "state_100mhz", "state_200mhz";
348 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
349 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
350 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
351 status = "okay";
352};