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git01.mediatek.com / filogic / uboot / 89a90d022a72f1bf4585a75220acec6a4f9e78bb / . / arch / arm / dts / fsl-imx8qm-apalis-u-boot.dtsi
blob: c54a59e89c5d158c43c78753785904771d42e1d1 [file] [log] [blame]
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * Copyright 2019 Toradex AG
4 */
5
6&mu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]7 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]8};
9
10&clk {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]11 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]12};
13
14&iomuxc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]15 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]16};
17
18&pd_lsio {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]19 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]20};
21
22&pd_lsio_gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]23 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]24};
25
26&pd_lsio_gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]28};
29
30&pd_lsio_gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]31 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]32};
33
34&pd_lsio_gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]35 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]36};
37
38&pd_lsio_gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]39 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]40};
41
42&pd_lsio_gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]43 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]44};
45
46&pd_lsio_gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]47 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]48};
49
50&pd_lsio_gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]51 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]52};
53
Igor Opaniukff829842020-03-27 12:28:15 +0200[diff] [blame]54&pd_dma {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]55 bootph-some-ram;
Igor Opaniukff829842020-03-27 12:28:15 +0200[diff] [blame]56};
57
58&pd_dma_lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]59 bootph-some-ram;
Igor Opaniukff829842020-03-27 12:28:15 +0200[diff] [blame]60};
61
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]62&pd_conn {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]64};
65
66&pd_conn_sdch0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]68};
69
70&pd_conn_sdch1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]71 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]72};
73
74&pd_conn_sdch2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]75 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]76};
77
78&gpio0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]79 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]80};
81
82&gpio1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]83 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]84};
85
86&gpio2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]88};
89
90&gpio3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]91 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]92};
93
94&gpio4 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-some-ram;
Andrejs Cainikovsb4c7eb62023-12-12 09:27:25 -0300[diff] [blame]96
97 usbh_en {
98 gpio-hog;
99 gpios = <4 GPIO_ACTIVE_HIGH>;
100 output-high;
101 };
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]102};
103
104&gpio5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]105 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]106};
107
108&gpio6 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]109 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]110};
111
112&gpio7 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]113 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]114};
115
116&lpuart0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]118};
119
120&lpuart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]122};
123
124&lpuart2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]125 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]126};
127
128&lpuart3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]130};
131
132&usdhc1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]133 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]134};
135
136&usdhc2 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]137 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]138};
139
140&usdhc3 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]141 bootph-some-ram;
Marcel Ziswiler475ceff2019-05-31 19:00:20 +0300[diff] [blame]142};