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git01.mediatek.com / filogic / uboot / 89a6593e6fa0e849d4d633e9c060f52ea909604d / . / board / bsh / imx6ulz_smm_m2 / spl.c
blob: 5b4812e129e3179d62dca64efd09cf501ccf77e1 [file] [log] [blame]
Michael Trimarchi273ab5a2022-09-18 17:09:53 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2
3#include <common.h>
4#include <cpu_func.h>
5#include <hang.h>
6#include <init.h>
7#include <asm/arch/clock.h>
8#include <asm/arch/iomux.h>
9#include <asm/arch/imx-regs.h>
10#include <asm/arch/crm_regs.h>
11#include <asm/arch/mx6ull_pins.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/gpio.h>
15#include <asm/mach-imx/iomux-v3.h>
16#include <asm/mach-imx/boot_mode.h>
17#include <linux/libfdt.h>
18#include <spl.h>
19#include <asm/arch/mx6-ddr.h>
20
21#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
22 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
23 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
24
25static const iomux_v3_cfg_t uart4_pads[] = {
26 MX6_PAD_UART4_TX_DATA__UART4_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
27 MX6_PAD_UART4_RX_DATA__UART4_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
28};
29
30static void setup_iomux_uart(void)
31{
32 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
33}
34
35static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
36 .grp_addds = 0x00000028,
37 .grp_ddrmode_ctl = 0x00020000,
38 .grp_b0ds = 0x00000028,
39 .grp_ctlds = 0x00000028,
40 .grp_b1ds = 0x00000028,
41 .grp_ddrpke = 0x00000000,
42 .grp_ddrmode = 0x00020000,
43 .grp_ddr_type = 0x000c0000,
44};
45
46static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
47 .dram_dqm0 = 0x00000028,
48 .dram_dqm1 = 0x00000028,
49 .dram_ras = 0x00000028,
50 .dram_cas = 0x00000028,
51 .dram_odt0 = 0x00000028,
52 .dram_odt1 = 0x00000028,
53 .dram_sdba2 = 0x00000000,
54 .dram_sdclk_0 = 0x00000028,
55 .dram_sdqs0 = 0x00000028,
56 .dram_sdqs1 = 0x00000028,
57 .dram_reset = 0x000c0028,
58};
59
60static struct mx6_mmdc_calibration mx6_mmcd_calib = {
61 .p0_mpwldectrl0 = 0x00000000,
62 .p0_mpwldectrl1 = 0x00100010,
63 .p0_mpdgctrl0 = 0x414c014c,
64 .p0_mpdgctrl1 = 0x00000000,
65 .p0_mprddlctl = 0x40403a42,
66 .p0_mpwrdlctl = 0x4040342e,
67};
68
69static struct mx6_ddr_sysinfo ddr_sysinfo = {
70 .dsize = 0,
71 .cs1_mirror = 0,
72 .cs_density = 32,
73 .ncs = 1,
74 .bi_on = 1,
75 .rtt_nom = 1,
76 .rtt_wr = 0,
77 .ralat = 5,
78 .walat = 1,
79 .mif3_mode = 3,
80 .rst_to_cke = 0x23, /* 33 cycles (JEDEC value for DDR3) - total of 500 us */
81 .sde_to_rst = 0x10, /* 14 cycles (JEDEC value for DDR3) - total of 200 us */
82 .refsel = 1,
83 .refr = 3,
84};
85
86static struct mx6_ddr3_cfg mem_ddr = {
87 .mem_speed = 1333,
88 .density = 2,
89 .width = 16,
90 .banks = 8,
91 .rowaddr = 13,
92 .coladdr = 10,
93 .pagesz = 2,
94 .trcd = 1350,
95 .trcmin = 4950,
96 .trasmin = 3600,
97};
98
99static void ccgr_init(void)
100{
101 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
102
103 writel(0xFFFFFFFF, &ccm->CCGR0);
104 writel(0xFFFFFFFF, &ccm->CCGR1);
105 writel(0xFFFFFFFF, &ccm->CCGR2);
106 writel(0xFFFFFFFF, &ccm->CCGR3);
107 writel(0xFFFFFFFF, &ccm->CCGR4);
108 writel(0xFFFFFFFF, &ccm->CCGR5);
109 writel(0xFFFFFFFF, &ccm->CCGR6);
110}
111
112static void imx6ul_spl_dram_cfg(void)
113{
114 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
115 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
116}
117
118void board_init_f(ulong dummy)
119{
120 ccgr_init();
121 arch_cpu_init();
122 timer_init();
123 setup_iomux_uart();
124 preloader_console_init();
125 imx6ul_spl_dram_cfg();
126}
127
128void reset_cpu(void)
129{
130}