| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
| 3 | * |
| Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 4 | * SPDX-License-Identifier: GPL-2.0+ |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <config.h> |
| 8 | #include <version.h> |
| 9 | |
| Dinh Nguyen | ad51f7c | 2012-10-04 06:46:02 +0000 | [diff] [blame] | 10 | /* Set up the platform, once the cpu has been initialized */ |
| 11 | .globl lowlevel_init |
| 12 | lowlevel_init: |
| 13 | |
| 14 | /* Remap */ |
| 15 | #ifdef CONFIG_SPL_BUILD |
| 16 | /* |
| 17 | * SPL : configure the remap (L3 NIC-301 GPV) |
| 18 | * so the on-chip RAM at lower memory instead ROM. |
| 19 | */ |
| 20 | ldr r0, =SOCFPGA_L3REGS_ADDRESS |
| 21 | mov r1, #0x19 |
| 22 | str r1, [r0] |
| 23 | #else |
| 24 | /* |
| 25 | * U-Boot : configure the remap (L3 NIC-301 GPV) |
| 26 | * so the SDRAM at lower memory instead on-chip RAM. |
| 27 | */ |
| 28 | ldr r0, =SOCFPGA_L3REGS_ADDRESS |
| 29 | mov r1, #0x2 |
| 30 | str r1, [r0] |
| 31 | |
| 32 | /* Private components security */ |
| 33 | |
| 34 | /* |
| 35 | * U-Boot : configure private timer, global timer and cpu |
| 36 | * component access as non secure for kernel stage (as required |
| 37 | * by kernel) |
| 38 | */ |
| 39 | mrc p15,4,r0,c15,c0,0 |
| 40 | add r1, r0, #0x54 |
| 41 | ldr r2, [r1] |
| 42 | orr r2, r2, #0xff |
| 43 | orr r2, r2, #0xf00 |
| 44 | str r2, [r1] |
| 45 | #endif /* #ifdef CONFIG_SPL_BUILD */ |
| 46 | mov pc, lr |