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git01.mediatek.com / filogic / uboot / 8981bff6fef71c763e71a8c6124a9110adc85e08 / . / board / mousse / u-boot.lds.rom
blob: f162ae365ba3e8db3cf0b4e8ccee6a34359460e6 [file] [log] [blame]
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +0200[diff] [blame]5 * SPDX-License-Identifier: GPL-2.0+
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]6 */
7
8OUTPUT_ARCH(powerpc)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]9/* Do we need any of these for elf?
10 __DYNAMIC = 0; */
11SECTIONS
12{
13 /* Read-only sections, merged into text segment: */
14 . = + SIZEOF_HEADERS;
15 .interp : { *(.interp) }
16 .hash : { *(.hash) }
17 .dynsym : { *(.dynsym) }
18 .dynstr : { *(.dynstr) }
19 .rel.text : { *(.rel.text) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]20 .rela.text : { *(.rela.text) }
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]21 .rel.data : { *(.rel.data) }
Wolfgang Denka1be4762008-05-20 16:00:29 +0200[diff] [blame]22 .rela.data : { *(.rela.data) }
23 .rel.rodata : { *(.rel.rodata) }
24 .rela.rodata : { *(.rela.rodata) }
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]25 .rel.got : { *(.rel.got) }
26 .rela.got : { *(.rela.got) }
27 .rel.ctors : { *(.rel.ctors) }
28 .rela.ctors : { *(.rela.ctors) }
29 .rel.dtors : { *(.rel.dtors) }
30 .rela.dtors : { *(.rela.dtors) }
31 .rel.bss : { *(.rel.bss) }
32 .rela.bss : { *(.rela.bss) }
33 .rel.plt : { *(.rel.plt) }
34 .rela.plt : { *(.rela.plt) }
35 .init : { *(.init) }
36 .plt : { *(.plt) }
37 .text :
38 {
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]39 arch/powerpc/cpu/mpc824x/start.o (.text)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]40 common/board.o (.text)
Stefan Roese88fbf932010-04-15 16:07:28 +0200[diff] [blame]41 arch/powerpc/lib/ppcstring.o (.text)
Peter Tyser685b7f52010-04-12 22:28:05 -0500[diff] [blame]42 lib/vsprintf.o (.text)
43 lib/crc32.o (.text)
44 lib/zlib.o (.text)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]45
46 . = env_offset;
Jean-Christophe PLAGNIOL-VILLARD4436c1e2008-09-10 22:48:01 +0200[diff] [blame]47 common/env_embedded.o (.text)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]48
49 *(.text)
50
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]51 *(.got1)
52 . = ALIGN(16);
53 *(.rodata)
54 *(.rodata1)
Wolfgang Denkaaa7c002005-12-12 16:06:05 +0100[diff] [blame]55 *(.rodata.str1.4)
56 *(.eh_frame)
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]57 }
58 .fini : { *(.fini) } =0
59 .ctors : { *(.ctors) }
60 .dtors : { *(.dtors) }
61
62 /* Read-write section, merged into data segment: */
63 . = (. + 0x0FF) & 0xFFFFFF00;
64 _erotext = .;
65 PROVIDE (erotext = .);
66 .reloc :
67 {
68 *(.got)
69 _GOT2_TABLE_ = .;
70 *(.got2)
71 _FIXUP_TABLE_ = .;
72 *(.fixup)
73 }
74 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
75 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
76
77 .data :
78 {
79 *(.data)
80 *(.data1)
81 *(.sdata)
82 *(.sdata2)
83 *(.dynamic)
84 CONSTRUCTORS
85 }
86 _edata = .;
87 PROVIDE (edata = .);
88
wdenk57b2d802003-06-27 21:31:46 +0000[diff] [blame]89
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]90 __start___ex_table = .;
91 __ex_table : { *(__ex_table) }
92 __stop___ex_table = .;
93
94 . = ALIGN(4096);
95 __init_begin = .;
96 .text.init : { *(.text.init) }
97 .data.init : { *(.data.init) }
98 . = ALIGN(4096);
99 __init_end = .;
100
101 __bss_start = .;
102 .bss :
103 {
104 *(.sbss) *(.scommon)
105 *(.dynbss)
106 *(.bss)
107 *(COMMON)
108 }
109
Albert ARIBAUD0198f9d2013-03-30 00:19:53 +0000[diff] [blame]110 __bss_end = . ;
wdenkefee1702002-07-20 20:14:13 +0000[diff] [blame]111 PROVIDE (end = .);
112}