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git01.mediatek.com / filogic / uboot / 8981bff6fef71c763e71a8c6124a9110adc85e08 / . / arch / arm / cpu / tegra124-common / pinmux.c
blob: a4ab4eae408f95723db53583bb7ed00b60e0dcfd [file] [log] [blame]
Tom Warren8981bff2014-01-24 12:46:15 -0700[diff] [blame^]1/*
2 * (C) Copyright 2013
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/* Tegra124 pin multiplexing functions */
9
10#include <common.h>
11#include <asm/io.h>
12#include <asm/arch/tegra.h>
13#include <asm/arch/pinmux.h>
14
15struct tegra_pingroup_desc {
16 const char *name;
17 enum pmux_func funcs[4];
18 enum pmux_func func_safe;
19 enum pmux_vddio vddio;
20 enum pmux_pin_io io;
21};
22
23#define PMUX_MUXCTL_SHIFT 0
24#define PMUX_PULL_SHIFT 2
25#define PMUX_TRISTATE_SHIFT 4
26#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
27#define PMUX_IO_SHIFT 5
28#define PMUX_OD_SHIFT 6
29#define PMUX_LOCK_SHIFT 7
30#define PMUX_IO_RESET_SHIFT 8
31#define PMUX_RCV_SEL_SHIFT 9
32
33#define PGRP_HSM_SHIFT 2
34#define PGRP_SCHMT_SHIFT 3
35#define PGRP_LPMD_SHIFT 4
36#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
37#define PGRP_DRVDN_SHIFT 12
38#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
39#define PGRP_DRVUP_SHIFT 20
40#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
41#define PGRP_SLWR_SHIFT 28
42#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
43#define PGRP_SLWF_SHIFT 30
44#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
45
46/* Convenient macro for defining pin group properties */
47#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
48 { \
49 .vddio = PMUX_VDDIO_ ## vdd, \
50 .funcs = { \
51 PMUX_FUNC_ ## f0, \
52 PMUX_FUNC_ ## f1, \
53 PMUX_FUNC_ ## f2, \
54 PMUX_FUNC_ ## f3, \
55 }, \
56 .func_safe = PMUX_FUNC_RSVD1, \
57 .io = PMUX_PIN_ ## iod, \
58 }
59
60/* Input and output pins */
61#define PINI(pg_name, vdd, f0, f1, f2, f3) \
62 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
63#define PINO(pg_name, vdd, f0, f1, f2, f3) \
64 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
65
66/* A pin group number which is not used */
67#define PIN_RESERVED \
68 PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
69
70const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
71 /* NAME VDD f0 f1 f2 f3 */
72 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
73 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
74 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
75 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
76 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
77 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
78 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
79 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
80 PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
81 PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
82 PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
83 PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
84 PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
85 PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
86 PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
87 PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
88 PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
89 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
90 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
91 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
92 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
93 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
94 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
95 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
96 PIN_RESERVED, /* Reserved: 0x3060 - 0x3064 */
97 PIN_RESERVED,
98 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
99 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
100 PIN_RESERVED, /* Reserved: 0x3070 - 0x310c */
101 PIN_RESERVED,
102 PIN_RESERVED,
103 PIN_RESERVED,
104 PIN_RESERVED,
105 PIN_RESERVED,
106 PIN_RESERVED,
107 PIN_RESERVED,
108 PIN_RESERVED,
109 PIN_RESERVED,
110 PIN_RESERVED,
111 PIN_RESERVED,
112 PIN_RESERVED,
113 PIN_RESERVED,
114 PIN_RESERVED,
115 PIN_RESERVED,
116 PIN_RESERVED,
117 PIN_RESERVED,
118 PIN_RESERVED,
119 PIN_RESERVED,
120 PIN_RESERVED,
121 PIN_RESERVED,
122 PIN_RESERVED,
123 PIN_RESERVED,
124 PIN_RESERVED,
125 PIN_RESERVED,
126 PIN_RESERVED,
127 PIN_RESERVED,
128 PIN_RESERVED,
129 PIN_RESERVED,
130 PIN_RESERVED,
131 PIN_RESERVED,
132 PIN_RESERVED,
133 PIN_RESERVED,
134 PIN_RESERVED,
135 PIN_RESERVED,
136 PIN_RESERVED,
137 PIN_RESERVED,
138 PIN_RESERVED,
139 PIN_RESERVED,
140 PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
141 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
142 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
143 PIN_RESERVED, /* Reserved: 0x311c - 0x3160 */
144 PIN_RESERVED,
145 PIN_RESERVED,
146 PIN_RESERVED,
147 PIN_RESERVED,
148 PIN_RESERVED,
149 PIN_RESERVED,
150 PIN_RESERVED,
151 PIN_RESERVED,
152 PIN_RESERVED,
153 PIN_RESERVED,
154 PIN_RESERVED,
155 PIN_RESERVED,
156 PIN_RESERVED,
157 PIN_RESERVED,
158 PIN_RESERVED,
159 PIN_RESERVED,
160 PIN_RESERVED,
161 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
162 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
163 PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
164 PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
165 PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
166 PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
167 PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
168 PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
169 PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
170 PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
171 PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
172 PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
173 PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
174 PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
175 PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
176 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
177 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
178 PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
179 PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
180 PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
181 PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
182 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
183 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
184 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
185 PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
186 PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
187 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
188 PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
189 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
190 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
191 PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
192 PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
193 PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
194 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
195 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
196 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
197 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
198 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
199 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
200 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
201 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
202 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
203 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
204 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
205 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
206 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
207 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
208 PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
209 PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
210 PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
211 PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
212 PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
213 PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
214 PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
215 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
216 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
217 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
218 PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
219 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
220 PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
221 PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
222 PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
223 PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
224 PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
225 PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
226 PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
227 PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
228 PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
229 PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
230 PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
231 PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
232 PIN_RESERVED, /* Reserved: 0x3280 */
233 PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
234 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
235 PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
236 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
237 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
238 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
239 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
240 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
241 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
242 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
243 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
244 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
245 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
246 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
247 PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
248 PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
249 PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
250 PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
251 PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
252 PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
253 PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
254 PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
255 PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
256 PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
257 PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
258 PIN_RESERVED, /* Reserved: 0x32e8 - 0x32f8 */
259 PIN_RESERVED,
260 PIN_RESERVED,
261 PIN_RESERVED,
262 PIN_RESERVED,
263 PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
264 PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
265 PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
266 PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
267 PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
268 PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
269 PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
270 PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
271 PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
272 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
273 PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
274 PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
275 PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
276 PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
277 PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
278 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
279 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
280 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
281 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
282 PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
283 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
284 PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
285 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
286 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
287 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
288 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
289 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
290 PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
291 PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
292 PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
293 PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
294 PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
295 PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
296 PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
297 PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
298 PIN_RESERVED, /* Reserved: 0x3388 - 0x338c */
299 PIN_RESERVED,
300 PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
301 PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
302 PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
303 PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
304 PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
305 PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
306 PIN_RESERVED, /* Reserved: 0x33a8 - 0x33dc */
307 PIN_RESERVED,
308 PIN_RESERVED,
309 PIN_RESERVED,
310 PIN_RESERVED,
311 PIN_RESERVED,
312 PIN_RESERVED,
313 PIN_RESERVED,
314 PIN_RESERVED,
315 PIN_RESERVED,
316 PIN_RESERVED,
317 PIN_RESERVED,
318 PIN_RESERVED,
319 PIN_RESERVED,
320 PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
321 PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
322 PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
323 PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
324 PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
325 PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
326 PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
327 PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
328 PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
329 PIN_RESERVED, /* Reserved: 0x3404 */
330 PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
331};
332
333void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
334{
335 struct pmux_tri_ctlr *pmt =
336 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
337 u32 *tri = &pmt->pmt_ctl[pin];
338 u32 reg;
339
340 /* Error check on pin */
341 assert(pmux_pingrp_isvalid(pin));
342
343 reg = readl(tri);
344 if (enable)
345 reg |= PMUX_TRISTATE_MASK;
346 else
347 reg &= ~PMUX_TRISTATE_MASK;
348 writel(reg, tri);
349}
350
351void pinmux_tristate_enable(enum pmux_pingrp pin)
352{
353 pinmux_set_tristate(pin, 1);
354}
355
356void pinmux_tristate_disable(enum pmux_pingrp pin)
357{
358 pinmux_set_tristate(pin, 0);
359}
360
361void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
362{
363 struct pmux_tri_ctlr *pmt =
364 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
365 u32 *pull = &pmt->pmt_ctl[pin];
366 u32 reg;
367
368 /* Error check on pin and pupd */
369 assert(pmux_pingrp_isvalid(pin));
370 assert(pmux_pin_pupd_isvalid(pupd));
371
372 reg = readl(pull);
373 reg &= ~(0x3 << PMUX_PULL_SHIFT);
374 reg |= (pupd << PMUX_PULL_SHIFT);
375 writel(reg, pull);
376}
377
378void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
379{
380 struct pmux_tri_ctlr *pmt =
381 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
382 u32 *muxctl = &pmt->pmt_ctl[pin];
383 int i, mux = -1;
384 u32 reg;
385
386 /* Error check on pin and func */
387 assert(pmux_pingrp_isvalid(pin));
388 assert(pmux_func_isvalid(func));
389
390 /* Handle special values */
391 if (func == PMUX_FUNC_SAFE)
392 func = tegra_soc_pingroups[pin].func_safe;
393
394 if (func & PMUX_FUNC_RSVD1) {
395 mux = func & 0x3;
396 } else {
397 /* Search for the appropriate function */
398 for (i = 0; i < 4; i++) {
399 if (tegra_soc_pingroups[pin].funcs[i] == func) {
400 mux = i;
401 break;
402 }
403 }
404 }
405 assert(mux != -1);
406
407 reg = readl(muxctl);
408 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
409 reg |= (mux << PMUX_MUXCTL_SHIFT);
410 writel(reg, muxctl);
411}
412
413void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
414{
415 struct pmux_tri_ctlr *pmt =
416 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
417 u32 *pin_io = &pmt->pmt_ctl[pin];
418 u32 reg;
419
420 /* Error check on pin and io */
421 assert(pmux_pingrp_isvalid(pin));
422 assert(pmux_pin_io_isvalid(io));
423
424 reg = readl(pin_io);
425 reg &= ~(0x1 << PMUX_IO_SHIFT);
426 reg |= (io & 0x1) << PMUX_IO_SHIFT;
427 writel(reg, pin_io);
428}
429
430static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
431{
432 struct pmux_tri_ctlr *pmt =
433 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
434 u32 *pin_lock = &pmt->pmt_ctl[pin];
435 u32 reg;
436
437 /* Error check on pin and lock */
438 assert(pmux_pingrp_isvalid(pin));
439 assert(pmux_pin_lock_isvalid(lock));
440
441 if (lock == PMUX_PIN_LOCK_DEFAULT)
442 return 0;
443
444 reg = readl(pin_lock);
445 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
446 if (lock == PMUX_PIN_LOCK_ENABLE) {
447 reg |= (0x1 << PMUX_LOCK_SHIFT);
448 } else {
449 /* lock == DISABLE, which isn't possible */
450 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
451 __func__, lock);
452 }
453 writel(reg, pin_lock);
454
455 return 0;
456}
457
458static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
459{
460 struct pmux_tri_ctlr *pmt =
461 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
462 u32 *pin_od = &pmt->pmt_ctl[pin];
463 u32 reg;
464
465 /* Error check on pin and od */
466 assert(pmux_pingrp_isvalid(pin));
467 assert(pmux_pin_od_isvalid(od));
468
469 if (od == PMUX_PIN_OD_DEFAULT)
470 return 0;
471
472 reg = readl(pin_od);
473 reg &= ~(0x1 << PMUX_OD_SHIFT);
474 if (od == PMUX_PIN_OD_ENABLE)
475 reg |= (0x1 << PMUX_OD_SHIFT);
476 writel(reg, pin_od);
477
478 return 0;
479}
480
481static int pinmux_set_ioreset(enum pmux_pingrp pin,
482 enum pmux_pin_ioreset ioreset)
483{
484 struct pmux_tri_ctlr *pmt =
485 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
486 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
487 u32 reg;
488
489 /* Error check on pin and ioreset */
490 assert(pmux_pingrp_isvalid(pin));
491 assert(pmux_pin_ioreset_isvalid(ioreset));
492
493 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
494 return 0;
495
496 reg = readl(pin_ioreset);
497 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
498 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
499 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
500 writel(reg, pin_ioreset);
501
502 return 0;
503}
504
505static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
506 enum pmux_pin_rcv_sel rcv_sel)
507{
508 struct pmux_tri_ctlr *pmt =
509 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
510 u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
511 u32 reg;
512
513 /* Error check on pin and rcv_sel */
514 assert(pmux_pingrp_isvalid(pin));
515 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
516
517 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
518 return 0;
519
520 reg = readl(pin_rcv_sel);
521 reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
522 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
523 reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
524 writel(reg, pin_rcv_sel);
525
526 return 0;
527}
528
529void pinmux_config_pingroup(struct pingroup_config *config)
530{
531 enum pmux_pingrp pin = config->pingroup;
532
533 pinmux_set_func(pin, config->func);
534 pinmux_set_pullupdown(pin, config->pull);
535 pinmux_set_tristate(pin, config->tristate);
536 pinmux_set_io(pin, config->io);
537 pinmux_set_lock(pin, config->lock);
538 pinmux_set_od(pin, config->od);
539 pinmux_set_ioreset(pin, config->ioreset);
540 pinmux_set_rcv_sel(pin, config->rcv_sel);
541}
542
543void pinmux_config_table(struct pingroup_config *config, int len)
544{
545 int i;
546
547 for (i = 0; i < len; i++)
548 pinmux_config_pingroup(&config[i]);
549}
550
551static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
552{
553 struct pmux_tri_ctlr *pmt =
554 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
555 u32 *pad_slwf = &pmt->pmt_drive[pad];
556 u32 reg;
557
558 /* Error check on pad and slwf */
559 assert(pmux_padgrp_isvalid(pad));
560 assert(pmux_pad_slw_isvalid(slwf));
561
562 /* NONE means unspecified/do not change/use POR value */
563 if (slwf == PGRP_SLWF_NONE)
564 return 0;
565
566 reg = readl(pad_slwf);
567 reg &= ~PGRP_SLWF_MASK;
568 reg |= (slwf << PGRP_SLWF_SHIFT);
569 writel(reg, pad_slwf);
570
571 return 0;
572}
573
574static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
575{
576 struct pmux_tri_ctlr *pmt =
577 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
578 u32 *pad_slwr = &pmt->pmt_drive[pad];
579 u32 reg;
580
581 /* Error check on pad and slwr */
582 assert(pmux_padgrp_isvalid(pad));
583 assert(pmux_pad_slw_isvalid(slwr));
584
585 /* NONE means unspecified/do not change/use POR value */
586 if (slwr == PGRP_SLWR_NONE)
587 return 0;
588
589 reg = readl(pad_slwr);
590 reg &= ~PGRP_SLWR_MASK;
591 reg |= (slwr << PGRP_SLWR_SHIFT);
592 writel(reg, pad_slwr);
593
594 return 0;
595}
596
597static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
598{
599 struct pmux_tri_ctlr *pmt =
600 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
601 u32 *pad_drvup = &pmt->pmt_drive[pad];
602 u32 reg;
603
604 /* Error check on pad and drvup */
605 assert(pmux_padgrp_isvalid(pad));
606 assert(pmux_pad_drv_isvalid(drvup));
607
608 /* NONE means unspecified/do not change/use POR value */
609 if (drvup == PGRP_DRVUP_NONE)
610 return 0;
611
612 reg = readl(pad_drvup);
613 reg &= ~PGRP_DRVUP_MASK;
614 reg |= (drvup << PGRP_DRVUP_SHIFT);
615 writel(reg, pad_drvup);
616
617 return 0;
618}
619
620static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
621{
622 struct pmux_tri_ctlr *pmt =
623 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
624 u32 *pad_drvdn = &pmt->pmt_drive[pad];
625 u32 reg;
626
627 /* Error check on pad and drvdn */
628 assert(pmux_padgrp_isvalid(pad));
629 assert(pmux_pad_drv_isvalid(drvdn));
630
631 /* NONE means unspecified/do not change/use POR value */
632 if (drvdn == PGRP_DRVDN_NONE)
633 return 0;
634
635 reg = readl(pad_drvdn);
636 reg &= ~PGRP_DRVDN_MASK;
637 reg |= (drvdn << PGRP_DRVDN_SHIFT);
638 writel(reg, pad_drvdn);
639
640 return 0;
641}
642
643static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
644{
645 struct pmux_tri_ctlr *pmt =
646 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
647 u32 *pad_lpmd = &pmt->pmt_drive[pad];
648 u32 reg;
649
650 /* Error check pad and lpmd value */
651 assert(pmux_padgrp_isvalid(pad));
652 assert(pmux_pad_lpmd_isvalid(lpmd));
653
654 /* NONE means unspecified/do not change/use POR value */
655 if (lpmd == PGRP_LPMD_NONE)
656 return 0;
657
658 reg = readl(pad_lpmd);
659 reg &= ~PGRP_LPMD_MASK;
660 reg |= (lpmd << PGRP_LPMD_SHIFT);
661 writel(reg, pad_lpmd);
662
663 return 0;
664}
665
666static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
667{
668 struct pmux_tri_ctlr *pmt =
669 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
670 u32 *pad_schmt = &pmt->pmt_drive[pad];
671 u32 reg;
672
673 /* Error check pad */
674 assert(pmux_padgrp_isvalid(pad));
675
676 /* NONE means unspecified/do not change/use POR value */
677 if (schmt == PGRP_SCHMT_NONE)
678 return 0;
679
680 reg = readl(pad_schmt);
681 reg &= ~(1 << PGRP_SCHMT_SHIFT);
682 if (schmt == PGRP_SCHMT_ENABLE)
683 reg |= (0x1 << PGRP_SCHMT_SHIFT);
684 writel(reg, pad_schmt);
685
686 return 0;
687}
688static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
689{
690 struct pmux_tri_ctlr *pmt =
691 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
692 u32 *pad_hsm = &pmt->pmt_drive[pad];
693 u32 reg;
694
695 /* Error check pad */
696 assert(pmux_padgrp_isvalid(pad));
697
698 /* NONE means unspecified/do not change/use POR value */
699 if (hsm == PGRP_HSM_NONE)
700 return 0;
701
702 reg = readl(pad_hsm);
703 reg &= ~(1 << PGRP_HSM_SHIFT);
704 if (hsm == PGRP_HSM_ENABLE)
705 reg |= (0x1 << PGRP_HSM_SHIFT);
706 writel(reg, pad_hsm);
707
708 return 0;
709}
710
711void padctrl_config_pingroup(struct padctrl_config *config)
712{
713 enum pdrive_pingrp pad = config->padgrp;
714
715 padgrp_set_drvup_slwf(pad, config->slwf);
716 padgrp_set_drvdn_slwr(pad, config->slwr);
717 padgrp_set_drvup(pad, config->drvup);
718 padgrp_set_drvdn(pad, config->drvdn);
719 padgrp_set_lpmd(pad, config->lpmd);
720 padgrp_set_schmt(pad, config->schmt);
721 padgrp_set_hsm(pad, config->hsm);
722}
723
724void padgrp_config_table(struct padctrl_config *config, int len)
725{
726 int i;
727
728 for (i = 0; i < len; i++)
729 padctrl_config_pingroup(&config[i]);
730}