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git01.mediatek.com / filogic / uboot / 8936edd8731b722c47b7737b5cf3019b1c04f1bd / . / arch / arm / dts / imx7d-smegw01.dts
blob: aefc654ad87d4ef4d03de6b90f8f70c026492666 [file] [log] [blame]
Fabio Estevamdb1aa292021-05-28 10:26:57 -0300[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2//
3// Copyright (C) 2020 PHYTEC Messtechnik GmbH
4// Author: Jens Lang <J.Lang@phytec.de>
5// Copyright (C) 2021 Fabio Estevam <festevam@denx.de>
6
7/dts-v1/;
8#include "imx7d.dtsi"
9
10/ {
11 model = "Storopack SMEGW01 board";
12 compatible = "storopack,imx7d-smegw01", "fsl,imx7d";
13
14 aliases {
15 mmc0 = &usdhc1;
16 mmc1 = &usdhc3;
17 };
18
19 chosen {
20 stdout-path = &uart1;
21 };
22
23 memory@80000000 {
24 device_type = "memory";
25 reg = <0x80000000 0x20000000>;
26 };
27};
28
29&fec1 {
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_enet1>;
32 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>,
33 <&clks IMX7D_ENET1_TIME_ROOT_CLK>;
34 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
35 assigned-clock-rates = <0>, <100000000>;
36 phy-mode = "rgmii-id";
37 phy-handle = <&ethphy0>;
38 fsl,magic-packet;
39 status = "okay";
40
41 mdio: mdio {
42 #address-cells = <1>;
43 #size-cells = <0>;
44
45 ethphy0: ethernet-phy@1 {
46 compatible = "ethernet-phy-ieee802.3-c22";
47 reg = <1>;
48 };
49 };
50};
51
52&uart1 {
53 pinctrl-names = "default";
54 pinctrl-0 = <&pinctrl_uart1>;
55 status = "okay";
56};
57
58&usdhc1 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_usdhc1>;
61 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
62 no-1-8-v;
63 enable-sdio-wakeup;
64 keep-power-in-suspend;
65 status = "okay";
66};
67
68&usdhc3 {
69 pinctrl-names = "default", "state_100mhz", "state_200mhz";
70 pinctrl-0 = <&pinctrl_usdhc3>;
71 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
72 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
73 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>;
74 assigned-clock-rates = <400000000>;
75 max-frequency = <200000000>;
76 bus-width = <8>;
77 fsl,tuning-step = <1>;
78 non-removable;
79 cap-sd-highspeed;
80 cap-mmc-highspeed;
81 cap-mmc-hw-reset;
82 mmc-hs200-1_8v;
83 mmc-ddr-1_8v;
84 sd-uhs-ddr50;
85 sd-uhs-sdr104;
86 status = "okay";
87};
88
89&wdog1 {
90 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_wdog>;
92 fsl,ext-reset-output;
93 status = "okay";
94};
95
96&iomuxc {
97 pinctrl_enet1: enet1grp {
98 fsl,pins = <
99 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x5
100 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x5
101 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x5
102 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x5
103 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x5
104 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x5
105 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x5
106 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x5
107 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x5
108 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x5
109 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x5
110 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x5
111 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x7
112 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x7
113 >;
114 };
115
116 pinctrl_uart1: uart1grp {
117 fsl,pins = <
118 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x74
119 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x7c
120 >;
121 };
122
123 pinctrl_usdhc1: usdhc1 {
124 fsl,pins = <
125 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59
126 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
127 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
128 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
129 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
130 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
131 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
132 >;
133 };
134
135 pinctrl_usdhc3: usdhc3 {
136 fsl,pins = <
137 MX7D_PAD_SD3_CMD__SD3_CMD 0x5d
138 MX7D_PAD_SD3_CLK__SD3_CLK 0x1d
139 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5d
140 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5d
141 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5d
142 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5d
143 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5d
144 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5d
145 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5d
146 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5d
147 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1d
148 >;
149 };
150
151 pinctrl_usdhc3_100mhz: usdhc3_100mhz {
152 fsl,pins = <
153 MX7D_PAD_SD3_CMD__SD3_CMD 0x5e
154 MX7D_PAD_SD3_CLK__SD3_CLK 0x1e
155 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5e
156 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5e
157 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5e
158 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5e
159 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5e
160 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5e
161 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5e
162 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5e
163 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1e
164 >;
165 };
166
167 pinctrl_usdhc3_200mhz: usdhc3_200mhz {
168 fsl,pins = <
169 MX7D_PAD_SD3_CMD__SD3_CMD 0x5f
170 MX7D_PAD_SD3_CLK__SD3_CLK 0x0f
171 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5f
172 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5f
173 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5f
174 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5f
175 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5f
176 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5f
177 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5f
178 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5f
179 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1f
180 >;
181 };
182};
183
184&iomuxc_lpsr {
185 pinctrl_wdog: wdoggrp {
186 fsl,pins = <
187 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74
188 >;
189 };
190};