blob: d614b704715f53aebc274e28c309e71417289078 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glassd2fdaaf2011-10-03 19:26:47 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
Simon Glassd2fdaaf2011-10-03 19:26:47 +00004 */
5
6#ifndef __CONFIG_H
7#define __CONFIG_H
8
Simon Glass1a4742c2016-07-04 11:57:52 -06009#ifndef CONFIG_SPL_BUILD
Simon Glass125a27b2014-06-11 23:29:43 -060010#define CONFIG_IO_TRACE
Simon Glass1a4742c2016-07-04 11:57:52 -060011#endif
Simon Glass125a27b2014-06-11 23:29:43 -060012
Thomas Chou7b059dc2015-10-30 15:35:52 +080013#ifndef CONFIG_TIMER
Rob Herring86bd4e82013-11-08 08:40:44 -060014#define CONFIG_SYS_TIMER_RATE 1000000
Thomas Chou7b059dc2015-10-30 15:35:52 +080015#endif
Rob Herring86bd4e82013-11-08 08:40:44 -060016
Henrik Nordström26f9a6c2013-11-10 10:26:56 -070017#define CONFIG_HOST_MAX_DEVICES 4
Simon Glasseb4cecd2012-12-26 09:53:37 +000018
Simon Glassc757cb02014-07-10 22:23:32 -060019#define CONFIG_MALLOC_F_ADDR 0x0010000
Simon Glassd2fdaaf2011-10-03 19:26:47 +000020
Simon Glassd2fdaaf2011-10-03 19:26:47 +000021#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
22
Simon Glassd2fdaaf2011-10-03 19:26:47 +000023/* turn on command-line edit/c/auto */
Simon Glassd2fdaaf2011-10-03 19:26:47 +000024
Simon Glass1f21d482014-09-15 06:33:20 -060025/* SPI - enable all SPI flash types for testing purposes */
Mike Frysinger494b82b2013-12-03 16:43:28 -070026
Simon Glass84640e82014-02-27 13:26:25 -070027#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
28
29#define CONFIG_PHYSMEM
Simon Glassd2fdaaf2011-10-03 19:26:47 +000030
31/* Size of our emulated memory */
Heinrich Schuchardtfff251e2020-06-07 18:47:35 +020032#define SB_CONCAT(x, y) x ## y
33#define SB_TO_UL(s) SB_CONCAT(s, UL)
Simon Glass62cf9122013-04-26 02:53:43 +000034#define CONFIG_SYS_SDRAM_BASE 0
Heinrich Schuchardtfff251e2020-06-07 18:47:35 +020035#define CONFIG_SYS_SDRAM_SIZE \
36 (SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
Simon Glass62cf9122013-04-26 02:53:43 +000037#define CONFIG_SYS_MONITOR_BASE 0
Simon Glassd2fdaaf2011-10-03 19:26:47 +000038
Simon Glassd2fdaaf2011-10-03 19:26:47 +000039#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
40 115200}
Simon Glassd2fdaaf2011-10-03 19:26:47 +000041
Sjoerd Simonsd0942242015-04-13 22:54:27 +020042#define BOOT_TARGET_DEVICES(func) \
43 func(HOST, host, 1) \
44 func(HOST, host, 0)
45
Simon Glass07bb5e72019-05-18 11:59:48 -060046#ifdef __ASSEMBLY__
47#define BOOTENV
48#else
Sjoerd Simonsd0942242015-04-13 22:54:27 +020049#include <config_distro_bootcmd.h>
Simon Glass07bb5e72019-05-18 11:59:48 -060050#endif
Simon Glassd2fdaaf2011-10-03 19:26:47 +000051
Joe Hershbergerc7dc2a32015-04-08 01:41:25 -050052#define CONFIG_KEEP_SERVERADDR
53#define CONFIG_UDP_CHECKSUM
Joe Hershbergerc7dc2a32015-04-08 01:41:25 -050054#define CONFIG_TIMESTAMP
Joe Hershbergerc96323f2015-03-22 17:09:22 -050055#define CONFIG_BOOTP_SERVERIP
Simon Glassd2fdaaf2011-10-03 19:26:47 +000056
Simon Glassdcc0bf42014-03-22 17:12:58 -060057#ifndef SANDBOX_NO_SDL
Simon Glass84640e82014-02-27 13:26:25 -070058#define CONFIG_SANDBOX_SDL
Simon Glassdcc0bf42014-03-22 17:12:58 -060059#endif
60
61/* LCD and keyboard require SDL support */
62#ifdef CONFIG_SANDBOX_SDL
Simon Glass84640e82014-02-27 13:26:25 -070063#define LCD_BPP LCD_COLOR16
Simon Glassf461f122014-10-15 04:53:04 -060064#define CONFIG_LCD_BMP_RLE8
Simon Glass84640e82014-02-27 13:26:25 -070065
Simon Glassdcc0bf42014-03-22 17:12:58 -060066#define CONFIG_KEYBOARD
67
Simon Glass2b510fa2015-11-08 23:48:07 -070068#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
Simon Glass798ff502016-01-21 19:44:51 -070069 "stdout=serial,vidconsole\0" \
70 "stderr=serial,vidconsole\0"
Simon Glassdcc0bf42014-03-22 17:12:58 -060071#else
Joe Hershberger6ab76992015-03-22 17:09:13 -050072#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
Simon Glass798ff502016-01-21 19:44:51 -070073 "stdout=serial,vidconsole\0" \
74 "stderr=serial,vidconsole\0"
Simon Glassdcc0bf42014-03-22 17:12:58 -060075#endif
Simon Glassd2fdaaf2011-10-03 19:26:47 +000076
Joe Hershberger6ab76992015-03-22 17:09:13 -050077#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
Claudiu Manoild9eaa922021-03-14 20:14:57 +080078 "eth2addr=00:00:11:22:33:48\0" \
Michael Walle7c41a222020-06-02 01:47:09 +020079 "eth3addr=00:00:11:22:33:45\0" \
Claudiu Manoild9eaa922021-03-14 20:14:57 +080080 "eth4addr=00:00:11:22:33:48\0" \
Michael Walle7c41a222020-06-02 01:47:09 +020081 "eth5addr=00:00:11:22:33:46\0" \
82 "eth6addr=00:00:11:22:33:47\0" \
Joe Hershberger6ab76992015-03-22 17:09:13 -050083 "ipaddr=1.2.3.4\0"
84
Sjoerd Simonsd0942242015-04-13 22:54:27 +020085#define MEM_LAYOUT_ENV_SETTINGS \
86 "bootm_size=0x10000000\0" \
87 "kernel_addr_r=0x1000000\0" \
88 "fdt_addr_r=0xc00000\0" \
89 "ramdisk_addr_r=0x2000000\0" \
90 "scriptaddr=0x1000\0" \
91 "pxefile_addr_r=0x2000\0"
92
93#define CONFIG_EXTRA_ENV_SETTINGS \
94 SANDBOX_SERIAL_SETTINGS \
95 SANDBOX_ETH_SETTINGS \
96 BOOTENV \
97 MEM_LAYOUT_ENV_SETTINGS
Joe Hershberger6ab76992015-03-22 17:09:13 -050098
Simon Glass1a4742c2016-07-04 11:57:52 -060099#ifndef CONFIG_SPL_BUILD
Simon Glass4e7227c2016-05-01 11:36:23 -0600100#define CONFIG_SYS_IDE_MAXBUS 1
101#define CONFIG_SYS_ATA_IDE0_OFFSET 0
102#define CONFIG_SYS_IDE_MAXDEVICE 2
103#define CONFIG_SYS_ATA_BASE_ADDR 0x100
104#define CONFIG_SYS_ATA_DATA_OFFSET 0
105#define CONFIG_SYS_ATA_REG_OFFSET 1
106#define CONFIG_SYS_ATA_ALT_OFFSET 2
107#define CONFIG_SYS_ATA_STRIDE 4
Simon Glass1a4742c2016-07-04 11:57:52 -0600108#endif
Simon Glass4e7227c2016-05-01 11:36:23 -0600109
Simon Glass151b9352016-05-01 11:36:25 -0600110#define CONFIG_SCSI_AHCI_PLAT
111#define CONFIG_SYS_SCSI_MAX_DEVICE 2
112#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
113#define CONFIG_SYS_SCSI_MAX_LUN 4
114
Simon Glass4a63e332016-05-01 11:36:27 -0600115#define CONFIG_SYS_SATA_MAX_DEVICE 2
116
Simon Glassd2fdaaf2011-10-03 19:26:47 +0000117#endif