blob: 5d6be26faa1c264896dde3ea528dc271cf5ec6c7 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Fabio Estevam891b8192016-04-18 09:56:16 -03002/*
3 * Copyright (C) 2015 Technexion Ltd.
4 *
5 * Author: Richard Hu <richard.hu@technexion.com>
Fabio Estevam891b8192016-04-18 09:56:16 -03006 */
7
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
Simon Glass274e0b02020-05-10 11:39:56 -06009#include <net.h>
Fabio Estevam891b8192016-04-18 09:56:16 -030010#include <asm/arch/clock.h>
11#include <asm/arch/iomux.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/mx6-pins.h>
15#include <asm/arch/sys_proto.h>
16#include <asm/gpio.h>
Stefano Babic33731bc2017-06-29 10:16:06 +020017#include <asm/mach-imx/iomux-v3.h>
Fabio Estevam891b8192016-04-18 09:56:16 -030018#include <asm/io.h>
19#include <common.h>
Diego Dortaf67d3042016-06-10 12:07:29 -030020#include <miiphy.h>
21#include <netdev.h>
Simon Glassdbd79542020-05-10 11:40:11 -060022#include <linux/delay.h>
Fabio Estevam891b8192016-04-18 09:56:16 -030023#include <linux/sizes.h>
24#include <usb.h>
Vanessa Maegima634601c2016-07-13 14:27:32 -030025#include <power/pmic.h>
26#include <power/pfuze3000_pmic.h>
27#include "../../freescale/common/pfuze.h"
Fabio Estevam891b8192016-04-18 09:56:16 -030028
29DECLARE_GLOBAL_DATA_PTR;
30
31#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
32 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
33 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
34
Fabio Estevam891b8192016-04-18 09:56:16 -030035#define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
37 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
38
Diego Dortaf67d3042016-06-10 12:07:29 -030039#define MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
40 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST | PAD_CTL_ODE)
41
42#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
43 PAD_CTL_SPEED_HIGH | \
44 PAD_CTL_DSE_48ohm | PAD_CTL_SRE_FAST)
45
46#define ENET_CLK_PAD_CTRL (PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
47
Fabio Estevame893c362019-09-09 22:23:39 -030048#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \
49 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
50
Diego Dortaf67d3042016-06-10 12:07:29 -030051#define RMII_PHY_RESET IMX_GPIO_NR(1, 28)
52
53static iomux_v3_cfg_t const fec_pads[] = {
54 MX6_PAD_ENET1_TX_EN__ENET2_MDC | MUX_PAD_CTRL(MDIO_PAD_CTRL),
55 MX6_PAD_ENET1_TX_DATA1__ENET2_MDIO | MUX_PAD_CTRL(MDIO_PAD_CTRL),
56 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
59 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_UART4_TX_DATA__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL),
65};
66
67static void setup_iomux_fec(void)
68{
69 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
70}
71
Masahiro Yamadaf7ed78b2020-06-26 15:13:33 +090072int board_eth_init(struct bd_info *bis)
Diego Dortaf67d3042016-06-10 12:07:29 -030073{
74 setup_iomux_fec();
75
Fabio Estevam28391c92019-02-14 10:01:49 -020076 gpio_request(RMII_PHY_RESET, "enet_phy_reset");
Diego Dortaf67d3042016-06-10 12:07:29 -030077 gpio_direction_output(RMII_PHY_RESET, 0);
78 /*
79 * According to KSZ8081MNX-RNB manual:
80 * For warm reset, the reset (RST#) pin should be asserted low for a
81 * minimum of 500μs. The strap-in pin values are read and updated
82 * at the de-assertion of reset.
83 */
84 udelay(500);
85
86 gpio_direction_output(RMII_PHY_RESET, 1);
87 /*
88 * According to KSZ8081MNX-RNB manual:
89 * After the de-assertion of reset, wait a minimum of 100μs before
90 * starting programming on the MIIM (MDC/MDIO) interface.
91 */
92 udelay(100);
93
94 return fecmxc_initialize(bis);
95}
96
97static int setup_fec(void)
98{
99 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
100 int ret;
101
102 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC2_MASK,
103 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK);
104
105 ret = enable_fec_anatop_clock(1, ENET_50MHZ);
106 if (ret)
107 return ret;
108
109 enable_enet_clk(1);
110
111 return 0;
112}
113
Fabio Estevame893c362019-09-09 22:23:39 -0300114#ifdef CONFIG_VIDEO_MXS
115static iomux_v3_cfg_t const lcd_pads[] = {
116 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
117 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
118 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
119 MX6_PAD_LCD_VSYNC__LCDIF_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
120 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
121 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
122 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
123 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
124 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
125 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
126 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
127 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
128 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
129 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
130 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
131 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
132 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
138 MX6_PAD_LCD_DATA18__LCDIF_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
139 MX6_PAD_LCD_DATA19__LCDIF_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
140 MX6_PAD_LCD_DATA20__LCDIF_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
141 MX6_PAD_LCD_DATA21__LCDIF_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
142 MX6_PAD_LCD_DATA22__LCDIF_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
143 MX6_PAD_LCD_DATA23__LCDIF_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
144 /* LCD_BLT_CTRL: GPIO for Brightness adjustment */
145 MX6_PAD_NAND_ALE__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
146 /* LCD_VDD_EN: LCD enabled */
147 MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
148};
149
150void setup_lcd(void)
151{
152 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
153 gpio_request(IMX_GPIO_NR(4, 10), "lcd_brightness");
154 gpio_request(IMX_GPIO_NR(1, 11), "lcd_enable");
155 /* Set Brightness to high */
156 gpio_direction_output(IMX_GPIO_NR(4, 10) , 1);
157 /* Set LCD enable to high */
158 gpio_direction_output(IMX_GPIO_NR(1, 11) , 1);
159}
160#endif
161
Diego Dortaf67d3042016-06-10 12:07:29 -0300162int board_phy_config(struct phy_device *phydev)
163{
164 phy_write(phydev, MDIO_DEVAD_NONE, 0x1f, 0x8190);
165
166 if (phydev->drv->config)
167 phydev->drv->config(phydev);
168
169 return 0;
170}
171
Fabio Estevam891b8192016-04-18 09:56:16 -0300172int dram_init(void)
173{
174 gd->ram_size = imx_ddr_size();
175
176 return 0;
177}
178
179static iomux_v3_cfg_t const uart6_pads[] = {
180 MX6_PAD_CSI_MCLK__UART6_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
181 MX6_PAD_CSI_PIXCLK__UART6_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
182};
183
Vanessa Maegimaf1ce9602016-06-13 13:01:38 -0300184#define USB_OTHERREGS_OFFSET 0x800
185#define UCTRL_PWR_POL (1 << 9)
186
Fabio Estevam891b8192016-04-18 09:56:16 -0300187static iomux_v3_cfg_t const usb_otg_pad[] = {
188 MX6_PAD_GPIO1_IO00__ANATOP_OTG1_ID | MUX_PAD_CTRL(OTG_ID_PAD_CTRL),
189};
190
191static void setup_iomux_uart(void)
192{
193 imx_iomux_v3_setup_multiple_pads(uart6_pads, ARRAY_SIZE(uart6_pads));
194}
195
196static void setup_usb(void)
197{
198 imx_iomux_v3_setup_multiple_pads(usb_otg_pad, ARRAY_SIZE(usb_otg_pad));
199}
200
Fabio Estevam891b8192016-04-18 09:56:16 -0300201int board_early_init_f(void)
202{
203 setup_iomux_uart();
204
205 return 0;
206}
Vanessa Maegima634601c2016-07-13 14:27:32 -0300207
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200208#ifdef CONFIG_DM_PMIC
Vanessa Maegima634601c2016-07-13 14:27:32 -0300209int power_init_board(void)
210{
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200211 struct udevice *dev;
212 int ret, dev_id, rev_id;
Vanessa Maegima634601c2016-07-13 14:27:32 -0300213
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200214 ret = pmic_get("pfuze3000", &dev);
215 if (ret == -ENODEV)
216 return 0;
217 if (ret != 0)
Vanessa Maegima634601c2016-07-13 14:27:32 -0300218 return ret;
219
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200220 dev_id = pmic_reg_read(dev, PFUZE3000_DEVICEID);
221 rev_id = pmic_reg_read(dev, PFUZE3000_REVID);
222 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
Vanessa Maegima634601c2016-07-13 14:27:32 -0300223
224 /* disable Low Power Mode during standby mode */
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200225 pmic_reg_write(dev, PFUZE3000_LDOGCTL, 0x1);
Vanessa Maegima634601c2016-07-13 14:27:32 -0300226
227 /* SW1B step ramp up time from 2us to 4us/25mV */
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200228 pmic_reg_write(dev, PFUZE3000_SW1BCONF, 0x40);
Vanessa Maegima634601c2016-07-13 14:27:32 -0300229
230 /* SW1B mode to APS/PFM */
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200231 pmic_reg_write(dev, PFUZE3000_SW1BMODE, 0xc);
Vanessa Maegima634601c2016-07-13 14:27:32 -0300232
233 /* SW1B standby voltage set to 0.975V */
Fabio Estevam49d4bf02019-02-14 10:01:50 -0200234 pmic_reg_write(dev, PFUZE3000_SW1BSTBY, 0xb);
Vanessa Maegima634601c2016-07-13 14:27:32 -0300235
236 return 0;
237}
238#endif
Fabio Estevam891b8192016-04-18 09:56:16 -0300239
240int board_usb_phy_mode(int port)
241{
Vanessa Maegimaf1ce9602016-06-13 13:01:38 -0300242 if (port == 1)
243 return USB_INIT_HOST;
244 else
245 return USB_INIT_DEVICE;
246}
247
248int board_ehci_hcd_init(int port)
249{
250 u32 *usbnc_usb_ctrl;
251
252 if (port > 1)
253 return -EINVAL;
254
255 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
256 port * 4);
257
258 /* Set Power polarity */
259 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
260
261 return 0;
Fabio Estevam891b8192016-04-18 09:56:16 -0300262}
263
264int board_init(void)
265{
266 /* Address of boot parameters */
267 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
268
Diego Dortaf67d3042016-06-10 12:07:29 -0300269 setup_fec();
Fabio Estevam891b8192016-04-18 09:56:16 -0300270 setup_usb();
Fabio Estevame893c362019-09-09 22:23:39 -0300271#ifdef CONFIG_VIDEO_MXS
272 setup_lcd();
273#endif
Fabio Estevam891b8192016-04-18 09:56:16 -0300274 return 0;
275}
276
277int checkboard(void)
278{
279 puts("Board: PICO-IMX6UL-EMMC\n");
280
281 return 0;
282}