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git01.mediatek.com / filogic / uboot / 88bf6d3fa5577c8f435a823b4a92c62c008b6936 / . / board / cloudengines / pogo_e02 / pogo_e02.c
blob: 8df039168c99947f90ebd76414570c960c3c2e4e [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]2/*
3 * Copyright (C) 2012
4 * David Purdy <david.c.purdy@gmail.com>
5 *
6 * Based on Kirkwood support:
7 * (C) Copyright 2009
8 * Marvell Semiconductor <www.marvell.com>
9 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]10 */
11
12#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -0600[diff] [blame]13#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -0600[diff] [blame]14#include <log.h>
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]15#include <miiphy.h>
Simon Glass0c364412019-12-28 10:44:48 -0700[diff] [blame]16#include <net.h>
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]17#include <asm/arch/cpu.h>
Stefan Roesec2437842014-10-22 12:13:06 +0200[diff] [blame]18#include <asm/arch/soc.h>
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]19#include <asm/arch/mpp.h>
20#include "pogo_e02.h"
21
22DECLARE_GLOBAL_DATA_PTR;
23
24int board_early_init_f(void)
25{
26 /*
27 * default gpio configuration
28 * There are maximum 64 gpios controlled through 2 sets of registers
29 * the below configuration configures mainly initial LED status
30 */
Stefan Roesec50ab392014-10-22 12:13:11 +0200[diff] [blame]31 mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
32 POGO_E02_OE_VAL_HIGH,
33 POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]34
35 /* Multi-Purpose Pins Functionality configuration */
Albert ARIBAUD4d424312012-11-26 11:27:36 +0000[diff] [blame]36 static const u32 kwmpp_config[] = {
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]37 MPP0_NF_IO2,
38 MPP1_NF_IO3,
39 MPP2_NF_IO4,
40 MPP3_NF_IO5,
41 MPP4_NF_IO6,
42 MPP5_NF_IO7,
43 MPP6_SYSRST_OUTn,
44 MPP7_GPO,
45 MPP8_UART0_RTS,
46 MPP9_UART0_CTS,
47 MPP10_UART0_TXD,
48 MPP11_UART0_RXD,
49 MPP12_SD_CLK,
50 MPP13_SD_CMD,
51 MPP14_SD_D0,
52 MPP15_SD_D1,
53 MPP16_SD_D2,
54 MPP17_SD_D3,
55 MPP18_NF_IO0,
56 MPP19_NF_IO1,
57 MPP29_TSMP9, /* USB Power Enable */
58 MPP48_GPIO, /* LED green */
59 MPP49_GPIO, /* LED orange */
60 0
61 };
Valentin Longchamp7d0d5022012-06-01 01:31:00 +0000[diff] [blame]62 kirkwood_mpp_conf(kwmpp_config, NULL);
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]63 return 0;
64}
65
66int board_init(void)
67{
68 /* Boot parameters address */
Stefan Roese0b741752014-10-22 12:13:13 +0200[diff] [blame]69 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
David Purdy415d07e2012-03-27 16:01:09 +0000[diff] [blame]70
71 return 0;
72}
73
74#ifdef CONFIG_RESET_PHY_R
75/* Configure and initialize PHY */
76void reset_phy(void)
77{
78 u16 reg;
79 u16 devadr;
80 char *name = "egiga0";
81
82 if (miiphy_set_current_dev(name))
83 return;
84
85 /* command to read PHY dev address */
86 if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
87 printf("Err..(%s) could not read PHY dev address\n", __func__);
88 return;
89 }
90
91 /*
92 * Enable RGMII delay on Tx and Rx for CPU port
93 * Ref: sec 4.7.2 of chip datasheet
94 */
95 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
96 miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
97 reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
98 miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
99 miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
100
101 /* reset the phy */
102 miiphy_reset(name, devadr);
103
104 debug("88E1116 Initialized on %s\n", name);
105}
106#endif /* CONFIG_RESET_PHY_R */