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Tom Warrenb7ea6d12014-01-24 12:46:13 -07001/*
2 * (C) Copyright 2010-2013
3 * NVIDIA Corporation <www.nvidia.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8/* Tegra124 clock control definitions */
9
10#ifndef _TEGRA124_CLOCK_H_
11#define _TEGRA124_CLOCK_H_
12
13#include <asm/arch-tegra/clock.h>
14
15/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
16#define OSC_FREQ_SHIFT 28
17#define OSC_FREQ_MASK (0xF << OSC_FREQ_SHIFT)
18
Simon Glass93a19952015-04-14 21:03:34 -060019/* CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0 */
20#define SOR0_CLK_SEL0 (1 << 14)
21#define SOR0_CLK_SEL1 (1 << 15)
22
Thierry Reding4bf98692014-12-09 22:25:06 -070023int tegra_plle_enable(void);
24
Simon Glass93a19952015-04-14 21:03:34 -060025void clock_sor_enable_edp_clock(void);
26
27/**
28 * clock_set_display_rate() - Set the display clock rate
29 *
30 * @frequency: the requested PLLD frequency
31 *
32 * Return the PLLD frequenc (which may not quite what was requested), or 0
33 * on failure
34 */
35u32 clock_set_display_rate(u32 frequency);
36
37/**
38 * clock_set_up_plldp() - Set up the EDP clock ready for use
39 */
40void clock_set_up_plldp(void);
41
Tom Warrenb7ea6d12014-01-24 12:46:13 -070042#endif /* _TEGRA124_CLOCK_H_ */